Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13414850	10184	0	0
alert_regwen_rd_A	13414850	4880	0	0
cpu_regwen_rd_A	13414850	4914	0	0
sw_rst_ctrl_n_0_rd_A	13414850	9932	0	0
sw_rst_ctrl_n_1_rd_A	13414850	10042	0	0
sw_rst_ctrl_n_2_rd_A	13414850	9699	0	0
sw_rst_ctrl_n_3_rd_A	13414850	9882	0	0
sw_rst_ctrl_n_4_rd_A	13414850	9751	0	0
sw_rst_ctrl_n_5_rd_A	13414850	9676	0	0
sw_rst_ctrl_n_6_rd_A	13414850	9689	0	0
sw_rst_ctrl_n_7_rd_A	13414850	9711	0	0
sw_rst_regwen_0_rd_A	13414850	5266	0	0
sw_rst_regwen_1_rd_A	13414850	5437	0	0
sw_rst_regwen_2_rd_A	13414850	5544	0	0
sw_rst_regwen_3_rd_A	13414850	5446	0	0
sw_rst_regwen_4_rd_A	13414850	5431	0	0
sw_rst_regwen_5_rd_A	13414850	5486	0	0
sw_rst_regwen_6_rd_A	13414850	5215	0	0
sw_rst_regwen_7_rd_A	13414850	5656	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	10184	0	0
T57	3191	20	0	0
T58	10559	2	0	0
T59	2751	253	0	0
T60	9889	698	0	0
T64	4128	10	0	0
T88	2729	304	0	0
T89	4525	23	0	0
T90	5332	18	0	0
T91	3755	9	0	0
T94	10735	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	4880	0	0
T16	1829	0	0	0
T35	25878	0	0	0
T43	48446	0	0	0
T86	0	224	0	0
T97	29859	38	0	0
T98	13437	0	0	0
T99	0	102	0	0
T101	1770	0	0	0
T102	3593	0	0	0
T103	0	113	0	0
T104	0	139	0	0
T105	0	50	0	0
T108	0	34	0	0
T128	0	33	0	0
T129	0	162	0	0
T130	0	71	0	0
T131	2692	0	0	0
T132	4061	0	0	0
T133	5601	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	4914	0	0
T16	1829	0	0	0
T35	25878	0	0	0
T43	48446	0	0	0
T86	0	210	0	0
T97	29859	34	0	0
T98	13437	0	0	0
T99	0	100	0	0
T101	1770	0	0	0
T102	3593	0	0	0
T103	0	124	0	0
T104	0	141	0	0
T105	0	77	0	0
T108	0	37	0	0
T128	0	30	0	0
T129	0	217	0	0
T130	0	45	0	0
T131	2692	0	0	0
T132	4061	0	0	0
T133	5601	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	9932	0	0
T4	5133	58	0	0
T5	1611	0	0	0
T6	4616	23	0	0
T7	2919	0	0	0
T8	17236	0	0	0
T9	49192	0	0	0
T10	3547	0	0	0
T11	11028	181	0	0
T12	2452	0	0	0
T14	5266	0	0	0
T30	0	147	0	0
T76	0	1	0	0
T86	0	395	0	0
T97	0	46	0	0
T99	0	124	0	0
T131	0	15	0	0
T134	0	4	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	10042	0	0
T4	5133	50	0	0
T5	1611	0	0	0
T6	4616	36	0	0
T7	2919	0	0	0
T8	17236	0	0	0
T9	49192	0	0	0
T10	3547	0	0	0
T11	11028	148	0	0
T12	2452	0	0	0
T14	5266	0	0	0
T30	0	134	0	0
T76	0	1	0	0
T86	0	326	0	0
T97	0	24	0	0
T99	0	172	0	0
T131	0	15	0	0
T134	0	2	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	9699	0	0
T4	5133	45	0	0
T5	1611	0	0	0
T6	4616	42	0	0
T7	2919	0	0	0
T8	17236	0	0	0
T9	49192	0	0	0
T10	3547	0	0	0
T11	11028	163	0	0
T12	2452	0	0	0
T14	5266	0	0	0
T30	0	135	0	0
T76	0	15	0	0
T86	0	340	0	0
T97	0	28	0	0
T99	0	122	0	0
T103	0	213	0	0
T131	0	15	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	9882	0	0
T4	5133	68	0	0
T5	1611	0	0	0
T6	4616	34	0	0
T7	2919	0	0	0
T8	17236	0	0	0
T9	49192	0	0	0
T10	3547	0	0	0
T11	11028	191	0	0
T12	2452	0	0	0
T14	5266	0	0	0
T30	0	159	0	0
T76	0	12	0	0
T86	0	317	0	0
T97	0	35	0	0
T99	0	140	0	0
T131	0	20	0	0
T134	0	3	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	9751	0	0
T4	5133	57	0	0
T5	1611	0	0	0
T6	4616	24	0	0
T7	2919	0	0	0
T8	17236	0	0	0
T9	49192	0	0	0
T10	3547	0	0	0
T11	11028	146	0	0
T12	2452	0	0	0
T14	5266	0	0	0
T30	0	130	0	0
T76	0	7	0	0
T86	0	291	0	0
T97	0	56	0	0
T99	0	112	0	0
T131	0	10	0	0
T134	0	2	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	9676	0	0
T4	5133	44	0	0
T5	1611	0	0	0
T6	4616	23	0	0
T7	2919	0	0	0
T8	17236	0	0	0
T9	49192	0	0	0
T10	3547	0	0	0
T11	11028	156	0	0
T12	2452	0	0	0
T14	5266	0	0	0
T30	0	153	0	0
T76	0	3	0	0
T86	0	337	0	0
T97	0	38	0	0
T99	0	133	0	0
T131	0	25	0	0
T134	0	3	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	9689	0	0
T4	5133	51	0	0
T5	1611	0	0	0
T6	4616	30	0	0
T7	2919	0	0	0
T8	17236	0	0	0
T9	49192	0	0	0
T10	3547	0	0	0
T11	11028	186	0	0
T12	2452	0	0	0
T14	5266	0	0	0
T30	0	150	0	0
T76	0	5	0	0
T86	0	327	0	0
T97	0	34	0	0
T99	0	163	0	0
T131	0	1	0	0
T134	0	1	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	9711	0	0
T4	5133	74	0	0
T5	1611	0	0	0
T6	4616	22	0	0
T7	2919	0	0	0
T8	17236	0	0	0
T9	49192	0	0	0
T10	3547	0	0	0
T11	11028	171	0	0
T12	2452	0	0	0
T14	5266	0	0	0
T30	0	161	0	0
T76	0	23	0	0
T86	0	310	0	0
T97	0	34	0	0
T99	0	164	0	0
T131	0	2	0	0
T134	0	6	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	5266	0	0
T11	11028	42	0	0
T12	2452	0	0	0
T13	25916	0	0	0
T14	5266	0	0	0
T15	4750	0	0	0
T30	0	34	0	0
T34	48892	0	0	0
T46	1695	0	0	0
T47	1481	0	0	0
T52	7313	0	0	0
T76	0	1	0	0
T81	2379	0	0	0
T86	0	243	0	0
T97	0	29	0	0
T99	0	91	0	0
T103	0	111	0	0
T104	0	124	0	0
T108	0	39	0	0
T135	0	26	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	5437	0	0
T11	11028	24	0	0
T12	2452	0	0	0
T13	25916	0	0	0
T14	5266	0	0	0
T15	4750	0	0	0
T30	0	33	0	0
T34	48892	0	0	0
T46	1695	0	0	0
T47	1481	0	0	0
T52	7313	0	0	0
T81	2379	0	0	0
T86	0	216	0	0
T97	0	35	0	0
T99	0	126	0	0
T103	0	118	0	0
T104	0	129	0	0
T105	0	83	0	0
T108	0	34	0	0
T135	0	26	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	5544	0	0
T11	11028	25	0	0
T12	2452	0	0	0
T13	25916	0	0	0
T14	5266	0	0	0
T15	4750	0	0	0
T30	0	30	0	0
T34	48892	0	0	0
T46	1695	0	0	0
T47	1481	0	0	0
T52	7313	0	0	0
T81	2379	0	0	0
T86	0	285	0	0
T97	0	23	0	0
T99	0	87	0	0
T103	0	152	0	0
T104	0	99	0	0
T105	0	51	0	0
T108	0	35	0	0
T135	0	32	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	5446	0	0
T11	11028	35	0	0
T12	2452	0	0	0
T13	25916	0	0	0
T14	5266	0	0	0
T15	4750	0	0	0
T30	0	28	0	0
T34	48892	0	0	0
T46	1695	0	0	0
T47	1481	0	0	0
T52	7313	0	0	0
T81	2379	0	0	0
T86	0	202	0	0
T97	0	41	0	0
T99	0	86	0	0
T103	0	127	0	0
T104	0	106	0	0
T105	0	83	0	0
T108	0	31	0	0
T135	0	26	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	5431	0	0
T11	11028	25	0	0
T12	2452	0	0	0
T13	25916	0	0	0
T14	5266	0	0	0
T15	4750	0	0	0
T30	0	29	0	0
T34	48892	0	0	0
T46	1695	0	0	0
T47	1481	0	0	0
T52	7313	0	0	0
T81	2379	0	0	0
T86	0	228	0	0
T97	0	37	0	0
T99	0	82	0	0
T103	0	116	0	0
T104	0	79	0	0
T105	0	86	0	0
T108	0	21	0	0
T135	0	22	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	5486	0	0
T11	11028	31	0	0
T12	2452	0	0	0
T13	25916	0	0	0
T14	5266	0	0	0
T15	4750	0	0	0
T30	0	35	0	0
T34	48892	0	0	0
T46	1695	0	0	0
T47	1481	0	0	0
T52	7313	0	0	0
T76	0	9	0	0
T81	2379	0	0	0
T86	0	221	0	0
T97	0	41	0	0
T99	0	125	0	0
T103	0	155	0	0
T104	0	117	0	0
T108	0	38	0	0
T135	0	26	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	5215	0	0
T11	11028	28	0	0
T12	2452	0	0	0
T13	25916	0	0	0
T14	5266	0	0	0
T15	4750	0	0	0
T30	0	21	0	0
T34	48892	0	0	0
T46	1695	0	0	0
T47	1481	0	0	0
T52	7313	0	0	0
T76	0	2	0	0
T81	2379	0	0	0
T86	0	215	0	0
T97	0	31	0	0
T99	0	85	0	0
T103	0	111	0	0
T104	0	107	0	0
T108	0	27	0	0
T135	0	34	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13414850	5656	0	0
T11	11028	37	0	0
T12	2452	0	0	0
T13	25916	0	0	0
T14	5266	0	0	0
T15	4750	0	0	0
T30	0	42	0	0
T34	48892	0	0	0
T46	1695	0	0	0
T47	1481	0	0	0
T52	7313	0	0	0
T76	0	2	0	0
T81	2379	0	0	0
T86	0	269	0	0
T97	0	52	0	0
T99	0	89	0	0
T103	0	148	0	0
T104	0	126	0	0
T108	0	37	0	0
T135	0	35	0	0