Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	651507	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

390487

1

T1

63

T3

73

T4

316

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	556898	1			T1	99		T3	99		T4	403
values[0x0]	241757	1			T1	50		T3	58		T4	175
values[0x1]	243339	1			T1	63		T3	55		T4	182

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	546576	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

495418

1

T1

81

T3

95

T4

384

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3628	1			T1	2		T4	5		T6	108
valid_sources[0x01]	7117	1			T6	133		T7	78		T8	1
valid_sources[0x02]	3239	1			T3	1		T4	2		T6	107
valid_sources[0x03]	3414	1			T4	4		T6	132		T7	47
valid_sources[0x04]	3805	1			T4	1		T6	106		T7	73
valid_sources[0x05]	3494	1			T1	2		T6	100		T7	73
valid_sources[0x06]	3318	1			T4	8		T6	154		T7	67
valid_sources[0x07]	4013	1			T3	1		T4	2		T6	108
valid_sources[0x08]	5574	1			T4	1		T6	120		T7	50
valid_sources[0x09]	4015	1			T3	3		T6	114		T7	78
valid_sources[0x0a]	3380	1			T3	1		T4	1		T6	127
valid_sources[0x0b]	4575	1			T4	10		T6	110		T7	70
valid_sources[0x0c]	3966	1			T1	1		T4	2		T6	125
valid_sources[0x0d]	4877	1			T4	3		T6	123		T7	62
valid_sources[0x0e]	4690	1			T3	1		T4	1		T6	103
valid_sources[0x0f]	3892	1			T1	1		T3	1		T4	3
valid_sources[0x10]	4598	1			T4	1		T6	125		T7	50
valid_sources[0x11]	4377	1			T3	1		T4	3		T6	113
valid_sources[0x12]	3586	1			T3	1		T4	2		T6	121
valid_sources[0x13]	3081	1			T1	12		T3	1		T4	3
valid_sources[0x14]	4561	1			T3	1		T4	6		T6	106
valid_sources[0x15]	3298	1			T3	2		T4	2		T6	132
valid_sources[0x16]	3368	1			T3	1		T4	1		T6	117
valid_sources[0x17]	3409	1			T3	2		T4	11		T6	127
valid_sources[0x18]	3898	1			T3	1		T4	1		T6	109
valid_sources[0x19]	4169	1			T4	5		T6	122		T7	51
valid_sources[0x1a]	4175	1			T4	3		T6	126		T7	69
valid_sources[0x1b]	4746	1			T4	9		T6	126		T7	69
valid_sources[0x1c]	4088	1			T3	1		T4	5		T6	128
valid_sources[0x1d]	3728	1			T1	4		T4	3		T6	136
valid_sources[0x1e]	4125	1			T3	1		T6	115		T7	56
valid_sources[0x1f]	7127	1			T3	3		T4	5		T6	124
valid_sources[0x20]	4301	1			T3	1		T4	3		T6	133
valid_sources[0x21]	3954	1			T6	106		T7	61		T8	2
valid_sources[0x22]	3705	1			T4	1		T6	129		T7	63
valid_sources[0x23]	4625	1			T4	1		T6	127		T7	55
valid_sources[0x24]	6902	1			T1	2		T4	1		T6	109
valid_sources[0x25]	3427	1			T6	113		T7	65		T8	1
valid_sources[0x26]	4217	1			T4	6		T6	131		T7	66
valid_sources[0x27]	3762	1			T3	1		T4	2		T6	131
valid_sources[0x28]	5164	1			T3	1		T4	1		T6	123
valid_sources[0x29]	3472	1			T4	3		T6	132		T7	66
valid_sources[0x2a]	3646	1			T6	147		T7	70		T8	4
valid_sources[0x2b]	4000	1			T3	3		T4	5		T6	114
valid_sources[0x2c]	3220	1			T6	109		T7	59		T10	31
valid_sources[0x2d]	6007	1			T4	3		T6	125		T7	66
valid_sources[0x2e]	4629	1			T1	1		T3	2		T4	7
valid_sources[0x2f]	3488	1			T3	1		T6	101		T7	65
valid_sources[0x30]	5582	1			T4	3		T6	126		T7	80
valid_sources[0x31]	4293	1			T1	2		T4	4		T6	112
valid_sources[0x32]	3392	1			T3	1		T4	2		T6	100
valid_sources[0x33]	3482	1			T3	1		T4	2		T6	125
valid_sources[0x34]	4035	1			T4	11		T6	118		T7	76
valid_sources[0x35]	3610	1			T4	5		T6	121		T7	86
valid_sources[0x36]	3357	1			T3	2		T4	1		T6	118
valid_sources[0x37]	3235	1			T4	4		T6	119		T7	59
valid_sources[0x38]	3918	1			T3	2		T4	4		T6	131
valid_sources[0x39]	4028	1			T4	3		T6	127		T7	51
valid_sources[0x3a]	4357	1			T6	115		T7	76		T8	1
valid_sources[0x3b]	4967	1			T3	3		T5	1		T6	119
valid_sources[0x3c]	3624	1			T4	2		T6	109		T7	63
valid_sources[0x3d]	3114	1			T3	1		T6	115		T7	75
valid_sources[0x3e]	4635	1			T3	1		T4	1		T6	117
valid_sources[0x3f]	6242	1			T3	2		T4	5		T6	100
valid_sources[0x40]	3820	1			T4	2		T6	124		T7	54
valid_sources[0x41]	4487	1			T3	2		T4	5		T6	117
valid_sources[0x42]	3859	1			T1	2		T3	1		T4	1
valid_sources[0x43]	3455	1			T4	5		T6	136		T7	65
valid_sources[0x44]	3436	1			T4	2		T6	116		T7	59
valid_sources[0x45]	3504	1			T1	7		T4	1		T6	103
valid_sources[0x46]	3346	1			T1	5		T3	2		T6	110
valid_sources[0x47]	4575	1			T3	1		T4	5		T6	108
valid_sources[0x48]	4512	1			T1	3		T4	1		T6	104
valid_sources[0x49]	4068	1			T4	4		T6	105		T7	70
valid_sources[0x4a]	3493	1			T4	4		T6	122		T7	58
valid_sources[0x4b]	3602	1			T3	1		T4	9		T6	113
valid_sources[0x4c]	3620	1			T1	4		T4	1		T6	118
valid_sources[0x4d]	4217	1			T4	3		T6	95		T7	64
valid_sources[0x4e]	6655	1			T3	1		T4	3		T6	122
valid_sources[0x4f]	4346	1			T1	4		T3	1		T4	6
valid_sources[0x50]	3639	1			T4	13		T6	128		T7	68
valid_sources[0x51]	3493	1			T1	3		T3	2		T6	128
valid_sources[0x52]	3507	1			T4	6		T6	129		T7	77
valid_sources[0x53]	3589	1			T3	1		T4	6		T6	122
valid_sources[0x54]	3700	1			T3	1		T4	1		T6	116
valid_sources[0x55]	3804	1			T4	7		T5	1		T6	116
valid_sources[0x56]	3642	1			T1	7		T3	1		T4	3
valid_sources[0x57]	3180	1			T1	1		T4	3		T6	121
valid_sources[0x58]	7572	1			T6	128		T7	55		T8	1
valid_sources[0x59]	3358	1			T1	3		T3	1		T4	9
valid_sources[0x5a]	3507	1			T3	2		T4	7		T6	124
valid_sources[0x5b]	4005	1			T3	2		T4	5		T6	126
valid_sources[0x5c]	4765	1			T4	6		T6	117		T7	66
valid_sources[0x5d]	4392	1			T4	9		T6	109		T7	47
valid_sources[0x5e]	3923	1			T6	113		T7	74		T10	46
valid_sources[0x5f]	3494	1			T3	3		T6	109		T7	54
valid_sources[0x60]	3890	1			T4	4		T6	134		T7	67
valid_sources[0x61]	3923	1			T1	4		T6	123		T7	64
valid_sources[0x62]	3532	1			T3	1		T4	2		T6	122
valid_sources[0x63]	3131	1			T6	140		T7	72		T8	4
valid_sources[0x64]	4449	1			T6	120		T7	69		T8	1
valid_sources[0x65]	3261	1			T1	2		T3	2		T4	2
valid_sources[0x66]	3636	1			T1	5		T3	1		T4	1
valid_sources[0x67]	3544	1			T4	3		T6	121		T7	71
valid_sources[0x68]	3690	1			T3	2		T4	1		T6	106
valid_sources[0x69]	4970	1			T3	1		T4	9		T6	125
valid_sources[0x6a]	6479	1			T3	2		T4	6		T6	104
valid_sources[0x6b]	5150	1			T4	16		T6	107		T7	59
valid_sources[0x6c]	3960	1			T6	101		T7	56		T8	2
valid_sources[0x6d]	3754	1			T3	2		T4	1		T6	129
valid_sources[0x6e]	3615	1			T1	6		T4	3		T6	120
valid_sources[0x6f]	4023	1			T3	1		T6	130		T7	62
valid_sources[0x70]	3979	1			T4	5		T5	1		T6	141
valid_sources[0x71]	3804	1			T3	2		T4	1		T6	120
valid_sources[0x72]	5016	1			T3	3		T4	1		T6	154
valid_sources[0x73]	3873	1			T3	2		T4	4		T6	118
valid_sources[0x74]	3788	1			T3	2		T6	125		T7	68
valid_sources[0x75]	4883	1			T1	1		T3	2		T5	1
valid_sources[0x76]	3768	1			T4	9		T6	104		T7	57
valid_sources[0x77]	3918	1			T4	2		T5	1		T6	114
valid_sources[0x78]	4049	1			T3	1		T6	125		T7	75
valid_sources[0x79]	3702	1			T1	1		T3	2		T5	1
valid_sources[0x7a]	3943	1			T3	1		T6	104		T7	58
valid_sources[0x7b]	3904	1			T4	6		T6	117		T7	65
valid_sources[0x7c]	3782	1			T1	3		T3	1		T6	120
valid_sources[0x7d]	3639	1			T3	1		T4	6		T6	133
valid_sources[0x7e]	3537	1			T1	1		T4	3		T6	93
valid_sources[0x7f]	3934	1			T3	1		T4	3		T6	136
valid_sources[0x80]	3416	1			T1	8		T4	1		T6	106

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

261234

1

T1

43

T3

39

T4

220

values[0x0]

all_enables

biggest_size

84342

1

T1

14

T3

23

T4

65

values[0x1]

all_enables

biggest_size

44911

1

T1

6

T3

11

T4

31