Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T6,T7,T9
1	0	Covered	T6,T7,T10

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55029810	9250	0	0
CascadeEffAonToRstPorAboveRise_A	55029810	9250	0	0
CascadeEffAonToRstPorIoAboveFall_A	52826302	9250	0	0
CascadeEffAonToRstPorIoAboveRise_A	52826302	9250	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26413982	9250	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26413982	9250	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13206831	9250	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13206831	9250	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26414077	9250	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26414077	9250	0	0
CascadeLcToLcAboveFall_A	55029810	23203	0	0
CascadeLcToLcAboveRise_A	55029810	23203	0	0
CascadeLcToLcAonAboveFall_A	1668905	23203	0	0
CascadeLcToLcAonAboveRise_A	1668905	23203	0	0
CascadeLcToLcShadowedAboveFall_A	55029810	23203	0	0
CascadeLcToLcShadowedAboveRise_A	55029810	23203	0	0
CascadePorToAonAboveFall_A	1668905	7280	0	0
CascadeSysToSysAboveFall_A	55029810	23203	0	0
CascadeSysToSysAboveRise_A	55029810	23203	0	0
ScanRstToAonRise_A	1668905	228	0	0
StablePorToAonRise_A	1668905	9250	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11632822	23203	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11632822	23203	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11632822	23203	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11632822	23203	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13206831	23203	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13206831	23203	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11632822	23203	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11632822	23203	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11632822	23203	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11632822	23203	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55029810	9250	0	0
T1	10782	2	0	0
T2	24263	8	0	0
T3	16906	2	0	0
T4	38596	1	0	0
T5	8638	1	0	0
T6	162627	204	0	0
T7	111141	108	0	0
T8	23596	2	0	0
T9	17587	2	0	0
T10	546563	66	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55029810	9250	0	0
T1	10782	2	0	0
T2	24263	8	0	0
T3	16906	2	0	0
T4	38596	1	0	0
T5	8638	1	0	0
T6	162627	204	0	0
T7	111141	108	0	0
T8	23596	2	0	0
T9	17587	2	0	0
T10	546563	66	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52826302	9250	0	0
T1	10350	2	0	0
T2	23290	8	0	0
T3	16224	2	0	0
T4	37051	1	0	0
T5	8292	1	0	0
T6	156120	204	0	0
T7	106691	108	0	0
T8	22648	2	0	0
T9	16883	2	0	0
T10	524662	66	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52826302	9250	0	0
T1	10350	2	0	0
T2	23290	8	0	0
T3	16224	2	0	0
T4	37051	1	0	0
T5	8292	1	0	0
T6	156120	204	0	0
T7	106691	108	0	0
T8	22648	2	0	0
T9	16883	2	0	0
T10	524662	66	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413982	9250	0	0
T1	5176	2	0	0
T2	11641	8	0	0
T3	8113	2	0	0
T4	18526	1	0	0
T5	4145	1	0	0
T6	780625	204	0	0
T7	533451	108	0	0
T8	11325	2	0	0
T9	8441	2	0	0
T10	262333	66	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413982	9250	0	0
T1	5176	2	0	0
T2	11641	8	0	0
T3	8113	2	0	0
T4	18526	1	0	0
T5	4145	1	0	0
T6	780625	204	0	0
T7	533451	108	0	0
T8	11325	2	0	0
T9	8441	2	0	0
T10	262333	66	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	9250	0	0
T1	2588	2	0	0
T2	5820	8	0	0
T3	4056	2	0	0
T4	9262	1	0	0
T5	2072	1	0	0
T6	390317	204	0	0
T7	266743	108	0	0
T8	5661	2	0	0
T9	4220	2	0	0
T10	131177	66	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	9250	0	0
T1	2588	2	0	0
T2	5820	8	0	0
T3	4056	2	0	0
T4	9262	1	0	0
T5	2072	1	0	0
T6	390317	204	0	0
T7	266743	108	0	0
T8	5661	2	0	0
T9	4220	2	0	0
T10	131177	66	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26414077	9250	0	0
T1	5173	2	0	0
T2	11642	8	0	0
T3	8115	2	0	0
T4	18525	1	0	0
T5	4145	1	0	0
T6	780631	204	0	0
T7	533478	108	0	0
T8	11323	2	0	0
T9	8443	2	0	0
T10	262347	66	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26414077	9250	0	0
T1	5173	2	0	0
T2	11642	8	0	0
T3	8115	2	0	0
T4	18525	1	0	0
T5	4145	1	0	0
T6	780631	204	0	0
T7	533478	108	0	0
T8	11323	2	0	0
T9	8443	2	0	0
T10	262347	66	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55029810	23203	0	0
T1	10782	6	0	0
T2	24263	8	0	0
T3	16906	6	0	0
T4	38596	1	0	0
T5	8638	1	0	0
T6	162627	602	0	0
T7	111141	332	0	0
T8	23596	6	0	0
T9	17587	6	0	0
T10	546563	172	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55029810	23203	0	0
T1	10782	6	0	0
T2	24263	8	0	0
T3	16906	6	0	0
T4	38596	1	0	0
T5	8638	1	0	0
T6	162627	602	0	0
T7	111141	332	0	0
T8	23596	6	0	0
T9	17587	6	0	0
T10	546563	172	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668905	23203	0	0
T1	323	6	0	0
T2	730	8	0	0
T3	507	6	0	0
T4	1155	1	0	0
T5	258	1	0	0
T6	49435	602	0	0
T7	33653	332	0	0
T8	707	6	0	0
T9	527	6	0	0
T10	16670	172	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668905	23203	0	0
T1	323	6	0	0
T2	730	8	0	0
T3	507	6	0	0
T4	1155	1	0	0
T5	258	1	0	0
T6	49435	602	0	0
T7	33653	332	0	0
T8	707	6	0	0
T9	527	6	0	0
T10	16670	172	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55029810	23203	0	0
T1	10782	6	0	0
T2	24263	8	0	0
T3	16906	6	0	0
T4	38596	1	0	0
T5	8638	1	0	0
T6	162627	602	0	0
T7	111141	332	0	0
T8	23596	6	0	0
T9	17587	6	0	0
T10	546563	172	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55029810	23203	0	0
T1	10782	6	0	0
T2	24263	8	0	0
T3	16906	6	0	0
T4	38596	1	0	0
T5	8638	1	0	0
T6	162627	602	0	0
T7	111141	332	0	0
T8	23596	6	0	0
T9	17587	6	0	0
T10	546563	172	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668905	7280	0	0
T1	323	1	0	0
T2	730	8	0	0
T3	507	1	0	0
T4	1155	1	0	0
T5	258	1	0	0
T6	49435	111	0	0
T7	33653	58	0	0
T8	707	1	0	0
T9	527	1	0	0
T10	16670	31	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55029810	23203	0	0
T1	10782	6	0	0
T2	24263	8	0	0
T3	16906	6	0	0
T4	38596	1	0	0
T5	8638	1	0	0
T6	162627	602	0	0
T7	111141	332	0	0
T8	23596	6	0	0
T9	17587	6	0	0
T10	546563	172	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55029810	23203	0	0
T1	10782	6	0	0
T2	24263	8	0	0
T3	16906	6	0	0
T4	38596	1	0	0
T5	8638	1	0	0
T6	162627	602	0	0
T7	111141	332	0	0
T8	23596	6	0	0
T9	17587	6	0	0
T10	546563	172	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668905	228	0	0
T6	49435	4	0	0
T7	33653	3	0	0
T8	707	0	0	0
T9	527	0	0	0
T10	16670	2	0	0
T11	3316	4	0	0
T12	400	0	0	0
T13	725	0	0	0
T23	728	0	0	0
T24	347	0	0	0
T26	0	3	0	0
T79	0	5	0	0
T81	0	7	0	0
T83	0	1	0	0
T85	0	1	0	0
T109	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668905	9250	0	0
T1	323	2	0	0
T2	730	8	0	0
T3	507	2	0	0
T4	1155	1	0	0
T5	258	1	0	0
T6	49435	204	0	0
T7	33653	108	0	0
T8	707	2	0	0
T9	527	2	0	0
T10	16670	66	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11632822	23203	0	0
T1	2391	6	0	0
T2	5469	8	0	0
T3	3956	6	0	0
T4	9171	1	0	0
T5	2053	1	0	0
T6	335678	602	0	0
T7	238826	332	0	0
T8	5373	6	0	0
T9	4076	6	0	0
T10	115228	172	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11632822	23203	0	0
T1	2391	6	0	0
T2	5469	8	0	0
T3	3956	6	0	0
T4	9171	1	0	0
T5	2053	1	0	0
T6	335678	602	0	0
T7	238826	332	0	0
T8	5373	6	0	0
T9	4076	6	0	0
T10	115228	172	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11632822	23203	0	0
T1	2391	6	0	0
T2	5469	8	0	0
T3	3956	6	0	0
T4	9171	1	0	0
T5	2053	1	0	0
T6	335678	602	0	0
T7	238826	332	0	0
T8	5373	6	0	0
T9	4076	6	0	0
T10	115228	172	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11632822	23203	0	0
T1	2391	6	0	0
T2	5469	8	0	0
T3	3956	6	0	0
T4	9171	1	0	0
T5	2053	1	0	0
T6	335678	602	0	0
T7	238826	332	0	0
T8	5373	6	0	0
T9	4076	6	0	0
T10	115228	172	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	23203	0	0
T1	2588	6	0	0
T2	5820	8	0	0
T3	4056	6	0	0
T4	9262	1	0	0
T5	2072	1	0	0
T6	390317	602	0	0
T7	266743	332	0	0
T8	5661	6	0	0
T9	4220	6	0	0
T10	131177	172	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	23203	0	0
T1	2588	6	0	0
T2	5820	8	0	0
T3	4056	6	0	0
T4	9262	1	0	0
T5	2072	1	0	0
T6	390317	602	0	0
T7	266743	332	0	0
T8	5661	6	0	0
T9	4220	6	0	0
T10	131177	172	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11632822	23203	0	0
T1	2391	6	0	0
T2	5469	8	0	0
T3	3956	6	0	0
T4	9171	1	0	0
T5	2053	1	0	0
T6	335678	602	0	0
T7	238826	332	0	0
T8	5373	6	0	0
T9	4076	6	0	0
T10	115228	172	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11632822	23203	0	0
T1	2391	6	0	0
T2	5469	8	0	0
T3	3956	6	0	0
T4	9171	1	0	0
T5	2053	1	0	0
T6	335678	602	0	0
T7	238826	332	0	0
T8	5373	6	0	0
T9	4076	6	0	0
T10	115228	172	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11632822	23203	0	0
T1	2391	6	0	0
T2	5469	8	0	0
T3	3956	6	0	0
T4	9171	1	0	0
T5	2053	1	0	0
T6	335678	602	0	0
T7	238826	332	0	0
T8	5373	6	0	0
T9	4076	6	0	0
T10	115228	172	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11632822	23203	0	0
T1	2391	6	0	0
T2	5469	8	0	0
T3	3956	6	0	0
T4	9171	1	0	0
T5	2053	1	0	0
T6	335678	602	0	0
T7	238826	332	0	0
T8	5373	6	0	0
T9	4076	6	0	0
T10	115228	172	0	0