Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13206831	14876	0	0
gen_assertions[0].RstEnOn_A	13206831	1081	0	0
gen_assertions[0].RstNOff_A	13206831	14876	0	0
gen_assertions[0].RstNOn_A	13206831	1081	0	0
gen_assertions[1].RstEnOff_A	52826302	13429	0	0
gen_assertions[1].RstEnOn_A	52826302	1008	0	0
gen_assertions[1].RstNOff_A	52826302	13429	0	0
gen_assertions[1].RstNOn_A	52826302	1008	0	0
gen_assertions[2].RstEnOff_A	26413982	13532	0	0
gen_assertions[2].RstEnOn_A	26413982	1048	0	0
gen_assertions[2].RstNOff_A	26413982	13532	0	0
gen_assertions[2].RstNOn_A	26413982	1048	0	0
gen_assertions[3].RstEnOff_A	26414077	13560	0	0
gen_assertions[3].RstEnOn_A	26414077	1068	0	0
gen_assertions[3].RstNOff_A	26414077	13560	0	0
gen_assertions[3].RstNOn_A	26414077	1068	0	0
gen_assertions[4].RstEnOff_A	1668905	22880	0	0
gen_assertions[4].RstEnOn_A	1668905	1132	0	0
gen_assertions[4].RstNOff_A	1668905	22880	0	0
gen_assertions[4].RstNOn_A	1668905	1132	0	0
gen_assertions[5].RstEnOff_A	13206831	15115	0	0
gen_assertions[5].RstEnOn_A	13206831	1202	0	0
gen_assertions[5].RstNOff_A	13206831	15115	0	0
gen_assertions[5].RstNOn_A	13206831	1202	0	0
gen_assertions[6].RstEnOff_A	13206831	15158	0	0
gen_assertions[6].RstEnOn_A	13206831	1250	0	0
gen_assertions[6].RstNOff_A	13206831	15158	0	0
gen_assertions[6].RstNOn_A	13206831	1250	0	0
gen_assertions[7].RstEnOff_A	13206831	15212	0	0
gen_assertions[7].RstEnOn_A	13206831	1304	0	0
gen_assertions[7].RstNOff_A	13206831	15212	0	0
gen_assertions[7].RstNOn_A	13206831	1304	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	14876	0	0
T1	2588	4	0	0
T2	5820	0	0	0
T3	4056	4	0	0
T4	9262	2	0	0
T5	2072	0	0	0
T6	390317	408	0	0
T7	266743	234	0	0
T8	5661	5	0	0
T9	4220	4	0	0
T10	131177	110	0	0
T11	0	36	0	0
T13	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	1081	0	0
T4	9262	2	0	0
T5	2072	0	0	0
T6	390317	11	0	0
T7	266743	12	0	0
T8	5661	1	0	0
T9	4220	0	0	0
T10	131177	4	0	0
T11	26234	0	0	0
T12	3207	0	0	0
T13	5808	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T26	0	4	0	0
T27	0	5	0	0
T28	0	10	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	14876	0	0
T1	2588	4	0	0
T2	5820	0	0	0
T3	4056	4	0	0
T4	9262	2	0	0
T5	2072	0	0	0
T6	390317	408	0	0
T7	266743	234	0	0
T8	5661	5	0	0
T9	4220	4	0	0
T10	131177	110	0	0
T11	0	36	0	0
T13	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	1081	0	0
T4	9262	2	0	0
T5	2072	0	0	0
T6	390317	11	0	0
T7	266743	12	0	0
T8	5661	1	0	0
T9	4220	0	0	0
T10	131177	4	0	0
T11	26234	0	0	0
T12	3207	0	0	0
T13	5808	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T26	0	4	0	0
T27	0	5	0	0
T28	0	10	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52826302	13429	0	0
T1	10350	4	0	0
T2	23290	0	0	0
T3	16224	4	0	0
T4	37051	3	0	0
T5	8292	0	0	0
T6	156120	372	0	0
T7	106691	206	0	0
T8	22648	4	0	0
T9	16883	4	0	0
T10	524662	105	0	0
T11	0	31	0	0
T13	0	3	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52826302	1008	0	0
T4	37051	3	0	0
T5	8292	0	0	0
T6	156120	10	0	0
T7	106691	9	0	0
T8	22648	0	0	0
T9	16883	0	0	0
T10	524662	5	0	0
T11	104922	0	0	0
T12	12833	0	0	0
T13	23236	1	0	0
T24	0	1	0	0
T25	0	3	0	0
T26	0	6	0	0
T27	0	7	0	0
T28	0	7	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52826302	13429	0	0
T1	10350	4	0	0
T2	23290	0	0	0
T3	16224	4	0	0
T4	37051	3	0	0
T5	8292	0	0	0
T6	156120	372	0	0
T7	106691	206	0	0
T8	22648	4	0	0
T9	16883	4	0	0
T10	524662	105	0	0
T11	0	31	0	0
T13	0	3	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52826302	1008	0	0
T4	37051	3	0	0
T5	8292	0	0	0
T6	156120	10	0	0
T7	106691	9	0	0
T8	22648	0	0	0
T9	16883	0	0	0
T10	524662	5	0	0
T11	104922	0	0	0
T12	12833	0	0	0
T13	23236	1	0	0
T24	0	1	0	0
T25	0	3	0	0
T26	0	6	0	0
T27	0	7	0	0
T28	0	7	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413982	13532	0	0
T1	5176	4	0	0
T2	11641	0	0	0
T3	8113	4	0	0
T4	18526	4	0	0
T5	4145	0	0	0
T6	780625	373	0	0
T7	533451	205	0	0
T8	11325	5	0	0
T9	8441	4	0	0
T10	262333	105	0	0
T11	0	31	0	0
T13	0	2	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413982	1048	0	0
T4	18526	4	0	0
T5	4145	0	0	0
T6	780625	11	0	0
T7	533451	8	0	0
T8	11325	1	0	0
T9	8441	0	0	0
T10	262333	5	0	0
T11	52468	0	0	0
T12	6415	0	0	0
T13	11617	0	0	0
T25	0	4	0	0
T26	0	5	0	0
T27	0	7	0	0
T28	0	6	0	0
T103	0	15	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413982	13532	0	0
T1	5176	4	0	0
T2	11641	0	0	0
T3	8113	4	0	0
T4	18526	4	0	0
T5	4145	0	0	0
T6	780625	373	0	0
T7	533451	205	0	0
T8	11325	5	0	0
T9	8441	4	0	0
T10	262333	105	0	0
T11	0	31	0	0
T13	0	2	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26413982	1048	0	0
T4	18526	4	0	0
T5	4145	0	0	0
T6	780625	11	0	0
T7	533451	8	0	0
T8	11325	1	0	0
T9	8441	0	0	0
T10	262333	5	0	0
T11	52468	0	0	0
T12	6415	0	0	0
T13	11617	0	0	0
T25	0	4	0	0
T26	0	5	0	0
T27	0	7	0	0
T28	0	6	0	0
T103	0	15	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26414077	13560	0	0
T1	5173	4	0	0
T2	11642	0	0	0
T3	8115	4	0	0
T4	18525	5	0	0
T5	4145	0	0	0
T6	780631	371	0	0
T7	533478	207	0	0
T8	11323	4	0	0
T9	8443	4	0	0
T10	262347	105	0	0
T11	0	31	0	0
T13	0	2	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26414077	1068	0	0
T4	18525	5	0	0
T5	4145	0	0	0
T6	780631	11	0	0
T7	533478	9	0	0
T8	11323	0	0	0
T9	8443	0	0	0
T10	262347	5	0	0
T11	52462	0	0	0
T12	6415	0	0	0
T13	11618	0	0	0
T25	0	7	0	0
T26	0	4	0	0
T27	0	8	0	0
T28	0	9	0	0
T79	0	26	0	0
T103	0	16	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26414077	13560	0	0
T1	5173	4	0	0
T2	11642	0	0	0
T3	8115	4	0	0
T4	18525	5	0	0
T5	4145	0	0	0
T6	780631	371	0	0
T7	533478	207	0	0
T8	11323	4	0	0
T9	8443	4	0	0
T10	262347	105	0	0
T11	0	31	0	0
T13	0	2	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26414077	1068	0	0
T4	18525	5	0	0
T5	4145	0	0	0
T6	780631	11	0	0
T7	533478	9	0	0
T8	11323	0	0	0
T9	8443	0	0	0
T10	262347	5	0	0
T11	52462	0	0	0
T12	6415	0	0	0
T13	11618	0	0	0
T25	0	7	0	0
T26	0	4	0	0
T27	0	8	0	0
T28	0	9	0	0
T79	0	26	0	0
T103	0	16	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668905	22880	0	0
T1	323	5	0	0
T2	730	3	0	0
T3	507	6	0	0
T4	1155	7	0	0
T5	258	1	0	0
T6	49435	609	0	0
T7	33653	336	0	0
T8	707	6	0	0
T9	527	6	0	0
T10	16670	174	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668905	1132	0	0
T4	1155	6	0	0
T5	258	0	0	0
T6	49435	10	0	0
T7	33653	12	0	0
T8	707	0	0	0
T9	527	0	0	0
T10	16670	2	0	0
T11	3316	0	0	0
T12	400	0	0	0
T13	725	0	0	0
T25	0	6	0	0
T26	0	4	0	0
T27	0	9	0	0
T28	0	9	0	0
T79	0	30	0	0
T103	0	13	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668905	22880	0	0
T1	323	5	0	0
T2	730	3	0	0
T3	507	6	0	0
T4	1155	7	0	0
T5	258	1	0	0
T6	49435	609	0	0
T7	33653	336	0	0
T8	707	6	0	0
T9	527	6	0	0
T10	16670	174	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668905	1132	0	0
T4	1155	6	0	0
T5	258	0	0	0
T6	49435	10	0	0
T7	33653	12	0	0
T8	707	0	0	0
T9	527	0	0	0
T10	16670	2	0	0
T11	3316	0	0	0
T12	400	0	0	0
T13	725	0	0	0
T25	0	6	0	0
T26	0	4	0	0
T27	0	9	0	0
T28	0	9	0	0
T79	0	30	0	0
T103	0	13	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	15115	0	0
T1	2588	4	0	0
T2	5820	0	0	0
T3	4056	4	0	0
T4	9262	8	0	0
T5	2072	0	0	0
T6	390317	410	0	0
T7	266743	234	0	0
T8	5661	4	0	0
T9	4220	4	0	0
T10	131177	111	0	0
T11	0	36	0	0
T13	0	5	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	1202	0	0
T4	9262	8	0	0
T5	2072	0	0	0
T6	390317	13	0	0
T7	266743	11	0	0
T8	5661	0	0	0
T9	4220	0	0	0
T10	131177	5	0	0
T11	26234	0	0	0
T12	3207	0	0	0
T13	5808	1	0	0
T24	0	1	0	0
T25	0	6	0	0
T26	0	3	0	0
T27	0	12	0	0
T28	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	15115	0	0
T1	2588	4	0	0
T2	5820	0	0	0
T3	4056	4	0	0
T4	9262	8	0	0
T5	2072	0	0	0
T6	390317	410	0	0
T7	266743	234	0	0
T8	5661	4	0	0
T9	4220	4	0	0
T10	131177	111	0	0
T11	0	36	0	0
T13	0	5	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	1202	0	0
T4	9262	8	0	0
T5	2072	0	0	0
T6	390317	13	0	0
T7	266743	11	0	0
T8	5661	0	0	0
T9	4220	0	0	0
T10	131177	5	0	0
T11	26234	0	0	0
T12	3207	0	0	0
T13	5808	1	0	0
T24	0	1	0	0
T25	0	6	0	0
T26	0	3	0	0
T27	0	12	0	0
T28	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	15158	0	0
T1	2588	4	0	0
T2	5820	0	0	0
T3	4056	4	0	0
T4	9262	8	0	0
T5	2072	0	0	0
T6	390317	411	0	0
T7	266743	233	0	0
T8	5661	4	0	0
T9	4220	4	0	0
T10	131177	109	0	0
T11	0	36	0	0
T13	0	5	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	1250	0	0
T4	9262	8	0	0
T5	2072	0	0	0
T6	390317	14	0	0
T7	266743	11	0	0
T8	5661	0	0	0
T9	4220	0	0	0
T10	131177	3	0	0
T11	26234	0	0	0
T12	3207	0	0	0
T13	5808	1	0	0
T24	0	1	0	0
T25	0	10	0	0
T26	0	6	0	0
T27	0	12	0	0
T28	0	7	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	15158	0	0
T1	2588	4	0	0
T2	5820	0	0	0
T3	4056	4	0	0
T4	9262	8	0	0
T5	2072	0	0	0
T6	390317	411	0	0
T7	266743	233	0	0
T8	5661	4	0	0
T9	4220	4	0	0
T10	131177	109	0	0
T11	0	36	0	0
T13	0	5	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	1250	0	0
T4	9262	8	0	0
T5	2072	0	0	0
T6	390317	14	0	0
T7	266743	11	0	0
T8	5661	0	0	0
T9	4220	0	0	0
T10	131177	3	0	0
T11	26234	0	0	0
T12	3207	0	0	0
T13	5808	1	0	0
T24	0	1	0	0
T25	0	10	0	0
T26	0	6	0	0
T27	0	12	0	0
T28	0	7	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	15212	0	0
T1	2588	4	0	0
T2	5820	0	0	0
T3	4056	4	0	0
T4	9262	9	0	0
T5	2072	0	0	0
T6	390317	409	0	0
T7	266743	234	0	0
T8	5661	4	0	0
T9	4220	4	0	0
T10	131177	108	0	0
T11	0	36	0	0
T13	0	5	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	1304	0	0
T4	9262	9	0	0
T5	2072	0	0	0
T6	390317	12	0	0
T7	266743	13	0	0
T8	5661	0	0	0
T9	4220	0	0	0
T10	131177	2	0	0
T11	26234	0	0	0
T12	3207	0	0	0
T13	5808	1	0	0
T25	0	11	0	0
T26	0	4	0	0
T27	0	13	0	0
T28	0	8	0	0
T103	0	16	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	15212	0	0
T1	2588	4	0	0
T2	5820	0	0	0
T3	4056	4	0	0
T4	9262	9	0	0
T5	2072	0	0	0
T6	390317	409	0	0
T7	266743	234	0	0
T8	5661	4	0	0
T9	4220	4	0	0
T10	131177	108	0	0
T11	0	36	0	0
T13	0	5	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13206831	1304	0	0
T4	9262	9	0	0
T5	2072	0	0	0
T6	390317	12	0	0
T7	266743	13	0	0
T8	5661	0	0	0
T9	4220	0	0	0
T10	131177	2	0	0
T11	26234	0	0	0
T12	3207	0	0	0
T13	5808	1	0	0
T25	0	11	0	0
T26	0	4	0	0
T27	0	13	0	0
T28	0	8	0	0
T103	0	16	0	0