Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12394419	9575	0	0
alert_regwen_rd_A	12394419	3748	0	0
cpu_regwen_rd_A	12394419	3798	0	0
sw_rst_ctrl_n_0_rd_A	12394419	8304	0	0
sw_rst_ctrl_n_1_rd_A	12394419	8484	0	0
sw_rst_ctrl_n_2_rd_A	12394419	8500	0	0
sw_rst_ctrl_n_3_rd_A	12394419	8662	0	0
sw_rst_ctrl_n_4_rd_A	12394419	8277	0	0
sw_rst_ctrl_n_5_rd_A	12394419	8523	0	0
sw_rst_ctrl_n_6_rd_A	12394419	8414	0	0
sw_rst_ctrl_n_7_rd_A	12394419	8442	0	0
sw_rst_regwen_0_rd_A	12394419	4564	0	0
sw_rst_regwen_1_rd_A	12394419	4631	0	0
sw_rst_regwen_2_rd_A	12394419	4300	0	0
sw_rst_regwen_3_rd_A	12394419	4596	0	0
sw_rst_regwen_4_rd_A	12394419	4475	0	0
sw_rst_regwen_5_rd_A	12394419	4714	0	0
sw_rst_regwen_6_rd_A	12394419	4510	0	0
sw_rst_regwen_7_rd_A	12394419	4445	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	9575	0	0
T66	4940	28	0	0
T68	3964	17	0	0
T69	10073	441	0	0
T70	10191	3	0	0
T71	14687	564	0	0
T87	9994	464	0	0
T97	4521	31	0	0
T105	3015	8	0	0
T106	9964	2	0	0
T107	4153	94	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	3748	0	0
T7	238826	293	0	0
T8	5373	0	0	0
T9	4076	0	0	0
T10	115228	127	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	0	0	0
T23	5072	0	0	0
T24	2452	0	0	0
T25	9789	0	0	0
T83	0	67	0	0
T85	0	97	0	0
T109	0	48	0	0
T111	0	66	0	0
T119	0	42	0	0
T120	0	250	0	0
T121	0	99	0	0
T122	0	147	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	3798	0	0
T7	238826	291	0	0
T8	5373	0	0	0
T9	4076	0	0	0
T10	115228	126	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	0	0	0
T23	5072	0	0	0
T24	2452	0	0	0
T25	9789	0	0	0
T83	0	76	0	0
T85	0	100	0	0
T109	0	37	0	0
T111	0	74	0	0
T119	0	51	0	0
T120	0	265	0	0
T121	0	127	0	0
T122	0	150	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	8304	0	0
T4	9171	137	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	404	0	0
T8	5373	7	0	0
T9	4076	0	0	0
T10	115228	202	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	11	0	0
T25	0	133	0	0
T27	0	175	0	0
T80	0	109	0	0
T83	0	89	0	0
T109	0	32	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	8484	0	0
T4	9171	122	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	400	0	0
T8	5373	7	0	0
T9	4076	0	0	0
T10	115228	161	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	14	0	0
T25	0	144	0	0
T27	0	183	0	0
T80	0	152	0	0
T83	0	73	0	0
T109	0	39	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	8500	0	0
T4	9171	138	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	438	0	0
T8	5373	13	0	0
T9	4076	0	0	0
T10	115228	127	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	7	0	0
T25	0	186	0	0
T27	0	198	0	0
T80	0	132	0	0
T83	0	92	0	0
T109	0	43	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	8662	0	0
T4	9171	151	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	447	0	0
T8	5373	18	0	0
T9	4076	0	0	0
T10	115228	190	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	13	0	0
T25	0	103	0	0
T27	0	179	0	0
T80	0	145	0	0
T83	0	67	0	0
T109	0	42	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	8277	0	0
T4	9171	138	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	450	0	0
T8	5373	12	0	0
T9	4076	0	0	0
T10	115228	172	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	13	0	0
T25	0	189	0	0
T27	0	185	0	0
T80	0	123	0	0
T83	0	80	0	0
T109	0	27	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	8523	0	0
T4	9171	157	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	446	0	0
T8	5373	13	0	0
T9	4076	0	0	0
T10	115228	125	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	14	0	0
T25	0	159	0	0
T27	0	194	0	0
T80	0	123	0	0
T83	0	66	0	0
T109	0	61	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	8414	0	0
T4	9171	139	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	462	0	0
T8	5373	13	0	0
T9	4076	0	0	0
T10	115228	201	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	22	0	0
T25	0	182	0	0
T27	0	202	0	0
T80	0	134	0	0
T83	0	80	0	0
T109	0	49	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	8442	0	0
T4	9171	157	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	439	0	0
T8	5373	9	0	0
T9	4076	0	0	0
T10	115228	117	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	11	0	0
T25	0	124	0	0
T27	0	206	0	0
T80	0	134	0	0
T83	0	88	0	0
T109	0	53	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	4564	0	0
T4	9171	42	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	289	0	0
T8	5373	4	0	0
T9	4076	0	0	0
T10	115228	120	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	4	0	0
T25	0	29	0	0
T27	0	31	0	0
T80	0	15	0	0
T83	0	69	0	0
T109	0	41	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	4631	0	0
T4	9171	31	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	304	0	0
T8	5373	0	0	0
T9	4076	0	0	0
T10	115228	173	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	12	0	0
T25	0	49	0	0
T27	0	36	0	0
T80	0	16	0	0
T83	0	82	0	0
T85	0	94	0	0
T109	0	26	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	4300	0	0
T4	9171	32	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	276	0	0
T8	5373	0	0	0
T9	4076	0	0	0
T10	115228	122	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	4	0	0
T25	0	30	0	0
T27	0	38	0	0
T80	0	32	0	0
T83	0	83	0	0
T85	0	113	0	0
T109	0	37	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	4596	0	0
T4	9171	43	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	300	0	0
T8	5373	3	0	0
T9	4076	0	0	0
T10	115228	130	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	8	0	0
T25	0	33	0	0
T27	0	39	0	0
T80	0	31	0	0
T83	0	52	0	0
T109	0	52	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	4475	0	0
T4	9171	33	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	290	0	0
T8	5373	9	0	0
T9	4076	0	0	0
T10	115228	141	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	13	0	0
T25	0	40	0	0
T27	0	20	0	0
T80	0	25	0	0
T83	0	81	0	0
T109	0	51	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	4714	0	0
T4	9171	33	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	342	0	0
T8	5373	2	0	0
T9	4076	0	0	0
T10	115228	145	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	1	0	0
T25	0	27	0	0
T27	0	22	0	0
T80	0	36	0	0
T83	0	77	0	0
T109	0	32	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	4510	0	0
T4	9171	43	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	314	0	0
T8	5373	1	0	0
T9	4076	0	0	0
T10	115228	151	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	2	0	0
T25	0	32	0	0
T27	0	31	0	0
T80	0	40	0	0
T83	0	96	0	0
T109	0	61	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12394419	4445	0	0
T4	9171	37	0	0
T5	2053	0	0	0
T6	335678	0	0	0
T7	238826	333	0	0
T8	5373	0	0	0
T9	4076	0	0	0
T10	115228	102	0	0
T11	20120	0	0	0
T12	3020	0	0	0
T13	5570	9	0	0
T25	0	39	0	0
T27	0	35	0	0
T80	0	33	0	0
T83	0	83	0	0
T85	0	98	0	0
T109	0	43	0	0