Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	639057	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

385967

1

T1

6925

T2

385

T3

75

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	548180	1			T1	10343		T2	547		T3	99
values[0x0]	237642	1			T1	4227		T2	247		T3	47
values[0x1]	239202	1			T1	4213		T2	254		T3	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	536208	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

488816

1

T1

8843

T2

484

T3

100

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4671	1			T1	80		T2	1		T6	1
valid_sources[0x01]	3404	1			T1	90		T2	5		T4	2
valid_sources[0x02]	3425	1			T1	94		T2	2		T7	3
valid_sources[0x03]	3878	1			T1	57		T2	5		T3	3
valid_sources[0x04]	3636	1			T1	64		T2	1		T3	1
valid_sources[0x05]	5090	1			T1	66		T2	5		T4	4
valid_sources[0x06]	3349	1			T1	63		T2	6		T3	3
valid_sources[0x07]	5671	1			T1	77		T2	4		T3	1
valid_sources[0x08]	3341	1			T1	59		T2	3		T4	4
valid_sources[0x09]	4245	1			T1	102		T2	3		T6	1
valid_sources[0x0a]	5282	1			T1	64		T2	7		T3	3
valid_sources[0x0b]	3679	1			T1	107		T2	2		T6	2
valid_sources[0x0c]	4077	1			T1	104		T2	4		T25	5
valid_sources[0x0d]	3203	1			T1	80		T2	3		T7	1
valid_sources[0x0e]	3662	1			T1	63		T2	2		T6	2
valid_sources[0x0f]	3636	1			T1	85		T2	9		T4	3
valid_sources[0x10]	4182	1			T1	109		T2	5		T4	10
valid_sources[0x11]	3381	1			T1	52		T2	8		T6	1
valid_sources[0x12]	4115	1			T1	67		T2	3		T3	1
valid_sources[0x13]	3109	1			T1	121		T2	2		T3	1
valid_sources[0x14]	3409	1			T1	94		T2	3		T3	1
valid_sources[0x15]	4773	1			T1	69		T2	4		T6	1
valid_sources[0x16]	3503	1			T1	65		T2	2		T6	1
valid_sources[0x17]	3738	1			T1	74		T2	8		T3	1
valid_sources[0x18]	4948	1			T1	64		T2	7		T6	1
valid_sources[0x19]	3992	1			T1	119		T2	4		T6	3
valid_sources[0x1a]	3213	1			T1	99		T2	3		T3	1
valid_sources[0x1b]	3511	1			T1	122		T2	4		T3	5
valid_sources[0x1c]	4213	1			T1	84		T2	3		T3	3
valid_sources[0x1d]	3626	1			T1	80		T2	3		T3	2
valid_sources[0x1e]	3230	1			T1	110		T2	6		T4	3
valid_sources[0x1f]	3575	1			T1	63		T2	1		T6	1
valid_sources[0x20]	3195	1			T1	89		T2	9		T3	6
valid_sources[0x21]	3839	1			T1	90		T2	2		T3	2
valid_sources[0x22]	3130	1			T1	34		T2	1		T3	1
valid_sources[0x23]	3047	1			T1	77		T2	5		T7	3
valid_sources[0x24]	3990	1			T1	68		T2	2		T3	1
valid_sources[0x25]	3119	1			T1	83		T2	2		T4	1
valid_sources[0x26]	3488	1			T1	76		T2	7		T4	4
valid_sources[0x27]	5398	1			T1	97		T2	3		T3	4
valid_sources[0x28]	7301	1			T1	55		T2	5		T6	1
valid_sources[0x29]	3078	1			T1	77		T2	2		T6	2
valid_sources[0x2a]	3285	1			T1	66		T2	4		T7	5
valid_sources[0x2b]	3950	1			T1	90		T2	9		T3	2
valid_sources[0x2c]	3284	1			T1	57		T2	4		T3	1
valid_sources[0x2d]	3584	1			T1	68		T2	2		T3	4
valid_sources[0x2e]	3852	1			T1	98		T2	4		T3	1
valid_sources[0x2f]	3744	1			T1	56		T2	7		T3	4
valid_sources[0x30]	5150	1			T1	83		T2	2		T7	3
valid_sources[0x31]	3515	1			T1	83		T2	4		T6	2
valid_sources[0x32]	4532	1			T1	75		T2	4		T3	3
valid_sources[0x33]	3920	1			T1	62		T2	5		T3	1
valid_sources[0x34]	3465	1			T1	72		T2	1		T4	4
valid_sources[0x35]	3728	1			T1	80		T2	7		T3	1
valid_sources[0x36]	3575	1			T1	48		T2	4		T7	2
valid_sources[0x37]	3952	1			T1	56		T2	5		T7	3
valid_sources[0x38]	3952	1			T1	73		T2	1		T7	2
valid_sources[0x39]	4912	1			T1	65		T2	4		T25	6
valid_sources[0x3a]	4541	1			T1	45		T2	2		T3	5
valid_sources[0x3b]	3431	1			T1	86		T2	5		T3	9
valid_sources[0x3c]	2927	1			T1	77		T2	2		T4	6
valid_sources[0x3d]	3378	1			T1	51		T2	7		T7	2
valid_sources[0x3e]	3992	1			T1	80		T2	3		T3	2
valid_sources[0x3f]	4656	1			T1	81		T2	8		T3	1
valid_sources[0x40]	4072	1			T1	85		T6	2		T7	3
valid_sources[0x41]	3444	1			T1	47		T2	8		T6	3
valid_sources[0x42]	4887	1			T1	61		T2	2		T3	7
valid_sources[0x43]	3995	1			T1	30		T2	9		T3	1
valid_sources[0x44]	3344	1			T1	80		T2	1		T6	3
valid_sources[0x45]	3082	1			T1	74		T2	5		T3	2
valid_sources[0x46]	3480	1			T1	72		T2	5		T3	2
valid_sources[0x47]	3346	1			T1	88		T2	4		T7	4
valid_sources[0x48]	3809	1			T1	81		T2	2		T3	1
valid_sources[0x49]	4051	1			T1	95		T2	9		T3	1
valid_sources[0x4a]	4351	1			T1	68		T2	4		T3	1
valid_sources[0x4b]	4712	1			T1	87		T2	6		T7	1
valid_sources[0x4c]	3374	1			T1	79		T2	8		T4	3
valid_sources[0x4d]	4083	1			T1	55		T2	3		T6	1
valid_sources[0x4e]	3426	1			T1	63		T2	3		T6	3
valid_sources[0x4f]	3335	1			T1	77		T7	1		T25	5
valid_sources[0x50]	3299	1			T1	109		T2	3		T7	2
valid_sources[0x51]	3471	1			T1	45		T2	2		T7	1
valid_sources[0x52]	3461	1			T1	68		T2	6		T7	8
valid_sources[0x53]	3069	1			T1	55		T2	2		T7	4
valid_sources[0x54]	4122	1			T1	79		T3	1		T4	2
valid_sources[0x55]	3435	1			T1	95		T2	7		T3	1
valid_sources[0x56]	3546	1			T1	70		T2	4		T6	2
valid_sources[0x57]	4535	1			T1	62		T2	8		T7	2
valid_sources[0x58]	4929	1			T1	68		T2	1		T7	5
valid_sources[0x59]	4119	1			T1	80		T2	9		T3	2
valid_sources[0x5a]	4711	1			T1	42		T2	3		T4	3
valid_sources[0x5b]	3420	1			T1	51		T2	3		T6	1
valid_sources[0x5c]	3186	1			T1	30		T2	1		T4	11
valid_sources[0x5d]	3399	1			T1	82		T2	3		T6	1
valid_sources[0x5e]	4684	1			T1	140		T2	1		T7	3
valid_sources[0x5f]	3343	1			T1	53		T2	1		T7	3
valid_sources[0x60]	4146	1			T1	51		T2	3		T7	1
valid_sources[0x61]	3327	1			T1	85		T2	4		T3	1
valid_sources[0x62]	3317	1			T1	85		T2	2		T3	3
valid_sources[0x63]	3191	1			T1	109		T2	7		T7	3
valid_sources[0x64]	4481	1			T1	67		T2	2		T6	4
valid_sources[0x65]	3787	1			T1	100		T2	3		T3	1
valid_sources[0x66]	3765	1			T1	70		T2	4		T3	2
valid_sources[0x67]	5476	1			T1	65		T2	6		T7	5
valid_sources[0x68]	4062	1			T1	96		T2	2		T3	2
valid_sources[0x69]	2791	1			T1	98		T2	6		T7	4
valid_sources[0x6a]	3345	1			T1	89		T2	3		T6	1
valid_sources[0x6b]	2893	1			T1	79		T2	2		T3	2
valid_sources[0x6c]	3672	1			T1	66		T2	2		T3	1
valid_sources[0x6d]	4126	1			T1	102		T2	5		T6	2
valid_sources[0x6e]	4083	1			T1	91		T2	6		T6	1
valid_sources[0x6f]	3162	1			T1	92		T2	5		T3	2
valid_sources[0x70]	3088	1			T1	65		T2	4		T3	3
valid_sources[0x71]	4141	1			T1	68		T2	4		T7	2
valid_sources[0x72]	4008	1			T1	65		T2	5		T25	1
valid_sources[0x73]	3561	1			T1	94		T2	8		T7	4
valid_sources[0x74]	3805	1			T1	102		T2	6		T7	4
valid_sources[0x75]	3555	1			T1	61		T2	6		T3	2
valid_sources[0x76]	4022	1			T1	77		T2	7		T3	1
valid_sources[0x77]	3558	1			T1	62		T2	2		T4	2
valid_sources[0x78]	5254	1			T1	102		T2	2		T6	1
valid_sources[0x79]	3737	1			T1	44		T2	4		T4	7
valid_sources[0x7a]	3620	1			T1	84		T2	2		T6	3
valid_sources[0x7b]	4749	1			T1	85		T2	7		T7	4
valid_sources[0x7c]	3553	1			T1	43		T2	2		T7	4
valid_sources[0x7d]	7516	1			T1	80		T2	5		T3	2
valid_sources[0x7e]	3627	1			T1	83		T7	1		T25	2
valid_sources[0x7f]	3372	1			T1	71		T2	5		T4	5
valid_sources[0x80]	3853	1			T1	80		T2	8		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

257721

1

T1

4782

T2

272

T3

48

values[0x0]

all_enables

biggest_size

83367

1

T1

1413

T2

76

T3

16

values[0x1]

all_enables

biggest_size

44879

1

T1

730

T2

37

T3

11