Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	12142224	13356	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	12142224	123331	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	12142224	7366896	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	12142224	196658	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	12142224	13356	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	12142224	123331	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	12142224	7366896	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	12142224	196658	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	13356	0	0
T1	207735	217	0	0
T2	8824	0	0	0
T3	3109	4	0	0
T4	3328	4	0	0
T5	5668	0	0	0
T6	3448	10	0	0
T7	8349	0	0	0
T8	11249	0	0	0
T9	1504	1	0	0
T10	1512	0	0	0
T11	0	75	0	0
T13	0	75	0	0
T14	0	171	0	0
T15	0	15	0	0
T28	0	226	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	123331	0	0
T1	207735	1965	0	0
T2	8824	0	0	0
T3	3109	38	0	0
T4	3328	37	0	0
T5	5668	0	0	0
T6	3448	90	0	0
T7	8349	0	0	0
T8	11249	0	0	0
T9	1504	9	0	0
T10	1512	0	0	0
T11	0	713	0	0
T13	0	718	0	0
T14	0	1578	0	0
T15	0	135	0	0
T28	0	2077	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	7366896	0	0
T1	207735	149882	0	0
T2	8824	8185	0	0
T3	3109	2139	0	0
T4	3328	2403	0	0
T5	5668	570	0	0
T6	3448	2644	0	0
T7	8349	7711	0	0
T8	11249	10604	0	0
T9	1504	895	0	0
T10	1512	939	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	196658	0	0
T1	207735	3202	0	0
T2	8824	0	0	0
T3	3109	70	0	0
T4	3328	55	0	0
T5	5668	0	0	0
T6	3448	159	0	0
T7	8349	0	0	0
T8	11249	0	0	0
T9	1504	17	0	0
T10	1512	0	0	0
T11	0	1123	0	0
T13	0	1077	0	0
T14	0	2556	0	0
T15	0	220	0	0
T28	0	3321	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	13356	0	0
T1	207735	217	0	0
T2	8824	0	0	0
T3	3109	4	0	0
T4	3328	4	0	0
T5	5668	0	0	0
T6	3448	10	0	0
T7	8349	0	0	0
T8	11249	0	0	0
T9	1504	1	0	0
T10	1512	0	0	0
T11	0	75	0	0
T13	0	75	0	0
T14	0	171	0	0
T15	0	15	0	0
T28	0	226	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	123331	0	0
T1	207735	1965	0	0
T2	8824	0	0	0
T3	3109	38	0	0
T4	3328	37	0	0
T5	5668	0	0	0
T6	3448	90	0	0
T7	8349	0	0	0
T8	11249	0	0	0
T9	1504	9	0	0
T10	1512	0	0	0
T11	0	713	0	0
T13	0	718	0	0
T14	0	1578	0	0
T15	0	135	0	0
T28	0	2077	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	7366896	0	0
T1	207735	149882	0	0
T2	8824	8185	0	0
T3	3109	2139	0	0
T4	3328	2403	0	0
T5	5668	570	0	0
T6	3448	2644	0	0
T7	8349	7711	0	0
T8	11249	10604	0	0
T9	1504	895	0	0
T10	1512	939	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	196658	0	0
T1	207735	3202	0	0
T2	8824	0	0	0
T3	3109	70	0	0
T4	3328	55	0	0
T5	5668	0	0	0
T6	3448	159	0	0
T7	8349	0	0	0
T8	11249	0	0	0
T9	1504	17	0	0
T10	1512	0	0	0
T11	0	1123	0	0
T13	0	1077	0	0
T14	0	2556	0	0
T15	0	220	0	0
T28	0	3321	0	0