Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T14,T28
1	0	Covered	T1,T14,T28

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	57072355	8922	0	0
CascadeEffAonToRstPorAboveRise_A	57072355	8922	0	0
CascadeEffAonToRstPorIoAboveFall_A	54787928	8922	0	0
CascadeEffAonToRstPorIoAboveRise_A	54787928	8922	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27394874	8922	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27394874	8922	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13696907	8922	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13696907	8922	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27394695	8922	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27394695	8922	0	0
CascadeLcToLcAboveFall_A	57072355	22278	0	0
CascadeLcToLcAboveRise_A	57072355	22278	0	0
CascadeLcToLcAonAboveFall_A	1729518	22278	0	0
CascadeLcToLcAonAboveRise_A	1729518	22278	0	0
CascadeLcToLcShadowedAboveFall_A	57072355	22278	0	0
CascadeLcToLcShadowedAboveRise_A	57072355	22278	0	0
CascadePorToAonAboveFall_A	1729518	6995	0	0
CascadeSysToSysAboveFall_A	57072355	22278	0	0
CascadeSysToSysAboveRise_A	57072355	22278	0	0
ScanRstToAonRise_A	1729518	206	0	0
StablePorToAonRise_A	1729518	8922	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12142224	22278	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12142224	22278	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12142224	22278	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12142224	22278	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13696907	22278	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13696907	22278	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12142224	22278	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12142224	22278	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12142224	22278	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12142224	22278	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57072355	8922	0	0
T1	984409	123	0	0
T2	36846	1	0	0
T3	14363	2	0	0
T4	15280	2	0	0
T5	24306	8	0	0
T6	17364	1	0	0
T7	34870	1	0	0
T8	46951	1	0	0
T9	6872	1	0	0
T10	6682	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57072355	8922	0	0
T1	984409	123	0	0
T2	36846	1	0	0
T3	14363	2	0	0
T4	15280	2	0	0
T5	24306	8	0	0
T6	17364	1	0	0
T7	34870	1	0	0
T8	46951	1	0	0
T9	6872	1	0	0
T10	6682	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54787928	8922	0	0
T1	945017	123	0	0
T2	35371	1	0	0
T3	13792	2	0	0
T4	14672	2	0	0
T5	23332	8	0	0
T6	16668	1	0	0
T7	33474	1	0	0
T8	45071	1	0	0
T9	6597	1	0	0
T10	6413	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54787928	8922	0	0
T1	945017	123	0	0
T2	35371	1	0	0
T3	13792	2	0	0
T4	14672	2	0	0
T5	23332	8	0	0
T6	16668	1	0	0
T7	33474	1	0	0
T8	45071	1	0	0
T9	6597	1	0	0
T10	6413	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394874	8922	0	0
T1	472500	123	0	0
T2	17685	1	0	0
T3	6895	2	0	0
T4	7336	2	0	0
T5	11665	8	0	0
T6	8334	1	0	0
T7	16737	1	0	0
T8	22535	1	0	0
T9	3298	1	0	0
T10	3206	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394874	8922	0	0
T1	472500	123	0	0
T2	17685	1	0	0
T3	6895	2	0	0
T4	7336	2	0	0
T5	11665	8	0	0
T6	8334	1	0	0
T7	16737	1	0	0
T8	22535	1	0	0
T9	3298	1	0	0
T10	3206	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	8922	0	0
T1	236258	123	0	0
T2	8841	1	0	0
T3	3445	2	0	0
T4	3665	2	0	0
T5	5829	8	0	0
T6	4167	1	0	0
T7	8367	1	0	0
T8	11267	1	0	0
T9	1649	1	0	0
T10	1602	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	8922	0	0
T1	236258	123	0	0
T2	8841	1	0	0
T3	3445	2	0	0
T4	3665	2	0	0
T5	5829	8	0	0
T6	4167	1	0	0
T7	8367	1	0	0
T8	11267	1	0	0
T9	1649	1	0	0
T10	1602	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394695	8922	0	0
T1	472520	123	0	0
T2	17685	1	0	0
T3	6897	2	0	0
T4	7333	2	0	0
T5	11658	8	0	0
T6	8334	1	0	0
T7	16737	1	0	0
T8	22536	1	0	0
T9	3297	1	0	0
T10	3206	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394695	8922	0	0
T1	472520	123	0	0
T2	17685	1	0	0
T3	6897	2	0	0
T4	7333	2	0	0
T5	11658	8	0	0
T6	8334	1	0	0
T7	16737	1	0	0
T8	22536	1	0	0
T9	3297	1	0	0
T10	3206	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57072355	22278	0	0
T1	984409	340	0	0
T2	36846	1	0	0
T3	14363	6	0	0
T4	15280	6	0	0
T5	24306	8	0	0
T6	17364	11	0	0
T7	34870	1	0	0
T8	46951	1	0	0
T9	6872	2	0	0
T10	6682	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57072355	22278	0	0
T1	984409	340	0	0
T2	36846	1	0	0
T3	14363	6	0	0
T4	15280	6	0	0
T5	24306	8	0	0
T6	17364	11	0	0
T7	34870	1	0	0
T8	46951	1	0	0
T9	6872	2	0	0
T10	6682	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1729518	22278	0	0
T1	29936	340	0	0
T2	1105	1	0	0
T3	429	6	0	0
T4	458	6	0	0
T5	730	8	0	0
T6	519	11	0	0
T7	1045	1	0	0
T8	1407	1	0	0
T9	205	2	0	0
T10	199	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1729518	22278	0	0
T1	29936	340	0	0
T2	1105	1	0	0
T3	429	6	0	0
T4	458	6	0	0
T5	730	8	0	0
T6	519	11	0	0
T7	1045	1	0	0
T8	1407	1	0	0
T9	205	2	0	0
T10	199	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57072355	22278	0	0
T1	984409	340	0	0
T2	36846	1	0	0
T3	14363	6	0	0
T4	15280	6	0	0
T5	24306	8	0	0
T6	17364	11	0	0
T7	34870	1	0	0
T8	46951	1	0	0
T9	6872	2	0	0
T10	6682	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57072355	22278	0	0
T1	984409	340	0	0
T2	36846	1	0	0
T3	14363	6	0	0
T4	15280	6	0	0
T5	24306	8	0	0
T6	17364	11	0	0
T7	34870	1	0	0
T8	46951	1	0	0
T9	6872	2	0	0
T10	6682	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1729518	6995	0	0
T1	29936	70	0	0
T2	1105	1	0	0
T3	429	1	0	0
T4	458	1	0	0
T5	730	8	0	0
T6	519	1	0	0
T7	1045	1	0	0
T8	1407	1	0	0
T9	205	1	0	0
T10	199	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57072355	22278	0	0
T1	984409	340	0	0
T2	36846	1	0	0
T3	14363	6	0	0
T4	15280	6	0	0
T5	24306	8	0	0
T6	17364	11	0	0
T7	34870	1	0	0
T8	46951	1	0	0
T9	6872	2	0	0
T10	6682	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57072355	22278	0	0
T1	984409	340	0	0
T2	36846	1	0	0
T3	14363	6	0	0
T4	15280	6	0	0
T5	24306	8	0	0
T6	17364	11	0	0
T7	34870	1	0	0
T8	46951	1	0	0
T9	6872	2	0	0
T10	6682	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1729518	206	0	0
T1	29936	7	0	0
T2	1105	0	0	0
T3	429	0	0	0
T4	458	0	0	0
T5	730	0	0	0
T6	519	0	0	0
T7	1045	0	0	0
T8	1407	0	0	0
T9	205	0	0	0
T10	199	0	0	0
T14	0	8	0	0
T28	0	3	0	0
T40	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T92	0	3	0	0
T93	0	2	0	0
T95	0	2	0	0
T100	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1729518	8922	0	0
T1	29936	123	0	0
T2	1105	1	0	0
T3	429	2	0	0
T4	458	2	0	0
T5	730	8	0	0
T6	519	1	0	0
T7	1045	1	0	0
T8	1407	1	0	0
T9	205	1	0	0
T10	199	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	22278	0	0
T1	207735	340	0	0
T2	8824	1	0	0
T3	3109	6	0	0
T4	3328	6	0	0
T5	5668	8	0	0
T6	3448	11	0	0
T7	8349	1	0	0
T8	11249	1	0	0
T9	1504	2	0	0
T10	1512	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	22278	0	0
T1	207735	340	0	0
T2	8824	1	0	0
T3	3109	6	0	0
T4	3328	6	0	0
T5	5668	8	0	0
T6	3448	11	0	0
T7	8349	1	0	0
T8	11249	1	0	0
T9	1504	2	0	0
T10	1512	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	22278	0	0
T1	207735	340	0	0
T2	8824	1	0	0
T3	3109	6	0	0
T4	3328	6	0	0
T5	5668	8	0	0
T6	3448	11	0	0
T7	8349	1	0	0
T8	11249	1	0	0
T9	1504	2	0	0
T10	1512	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	22278	0	0
T1	207735	340	0	0
T2	8824	1	0	0
T3	3109	6	0	0
T4	3328	6	0	0
T5	5668	8	0	0
T6	3448	11	0	0
T7	8349	1	0	0
T8	11249	1	0	0
T9	1504	2	0	0
T10	1512	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	22278	0	0
T1	236258	340	0	0
T2	8841	1	0	0
T3	3445	6	0	0
T4	3665	6	0	0
T5	5829	8	0	0
T6	4167	11	0	0
T7	8367	1	0	0
T8	11267	1	0	0
T9	1649	2	0	0
T10	1602	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	22278	0	0
T1	236258	340	0	0
T2	8841	1	0	0
T3	3445	6	0	0
T4	3665	6	0	0
T5	5829	8	0	0
T6	4167	11	0	0
T7	8367	1	0	0
T8	11267	1	0	0
T9	1649	2	0	0
T10	1602	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	22278	0	0
T1	207735	340	0	0
T2	8824	1	0	0
T3	3109	6	0	0
T4	3328	6	0	0
T5	5668	8	0	0
T6	3448	11	0	0
T7	8349	1	0	0
T8	11249	1	0	0
T9	1504	2	0	0
T10	1512	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	22278	0	0
T1	207735	340	0	0
T2	8824	1	0	0
T3	3109	6	0	0
T4	3328	6	0	0
T5	5668	8	0	0
T6	3448	11	0	0
T7	8349	1	0	0
T8	11249	1	0	0
T9	1504	2	0	0
T10	1512	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	22278	0	0
T1	207735	340	0	0
T2	8824	1	0	0
T3	3109	6	0	0
T4	3328	6	0	0
T5	5668	8	0	0
T6	3448	11	0	0
T7	8349	1	0	0
T8	11249	1	0	0
T9	1504	2	0	0
T10	1512	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12142224	22278	0	0
T1	207735	340	0	0
T2	8824	1	0	0
T3	3109	6	0	0
T4	3328	6	0	0
T5	5668	8	0	0
T6	3448	11	0	0
T7	8349	1	0	0
T8	11249	1	0	0
T9	1504	2	0	0
T10	1512	1	0	0