Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13696907	14342	0	0
gen_assertions[0].RstEnOn_A	13696907	1139	0	0
gen_assertions[0].RstNOff_A	13696907	14342	0	0
gen_assertions[0].RstNOn_A	13696907	1139	0	0
gen_assertions[1].RstEnOff_A	54787928	13062	0	0
gen_assertions[1].RstEnOn_A	54787928	1130	0	0
gen_assertions[1].RstNOff_A	54787928	13062	0	0
gen_assertions[1].RstNOn_A	54787928	1130	0	0
gen_assertions[2].RstEnOff_A	27394874	13069	0	0
gen_assertions[2].RstEnOn_A	27394874	1081	0	0
gen_assertions[2].RstNOff_A	27394874	13069	0	0
gen_assertions[2].RstNOn_A	27394874	1081	0	0
gen_assertions[3].RstEnOff_A	27394695	13166	0	0
gen_assertions[3].RstEnOn_A	27394695	1172	0	0
gen_assertions[3].RstNOff_A	27394695	13166	0	0
gen_assertions[3].RstNOn_A	27394695	1172	0	0
gen_assertions[4].RstEnOff_A	1729518	22199	0	0
gen_assertions[4].RstEnOn_A	1729518	1196	0	0
gen_assertions[4].RstNOff_A	1729518	22199	0	0
gen_assertions[4].RstNOn_A	1729518	1196	0	0
gen_assertions[5].RstEnOff_A	13696907	14602	0	0
gen_assertions[5].RstEnOn_A	13696907	1289	0	0
gen_assertions[5].RstNOff_A	13696907	14602	0	0
gen_assertions[5].RstNOn_A	13696907	1289	0	0
gen_assertions[6].RstEnOff_A	13696907	14624	0	0
gen_assertions[6].RstEnOn_A	13696907	1299	0	0
gen_assertions[6].RstNOff_A	13696907	14624	0	0
gen_assertions[6].RstNOn_A	13696907	1299	0	0
gen_assertions[7].RstEnOff_A	13696907	14681	0	0
gen_assertions[7].RstEnOn_A	13696907	1358	0	0
gen_assertions[7].RstNOff_A	13696907	14681	0	0
gen_assertions[7].RstNOn_A	13696907	1358	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	14342	0	0
T1	236258	248	0	0
T2	8841	2	0	0
T3	3445	4	0	0
T4	3665	4	0	0
T5	5829	0	0	0
T6	4167	10	0	0
T7	8367	1	0	0
T8	11267	5	0	0
T9	1649	1	0	0
T10	1602	0	0	0
T11	0	75	0	0
T25	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	1139	0	0
T1	236258	34	0	0
T2	8841	2	0	0
T3	3445	0	0	0
T4	3665	0	0	0
T5	5829	0	0	0
T6	4167	0	0	0
T7	8367	1	0	0
T8	11267	5	0	0
T9	1649	0	0	0
T10	1602	0	0	0
T14	0	23	0	0
T15	0	4	0	0
T25	0	5	0	0
T28	0	15	0	0
T30	0	12	0	0
T40	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	14342	0	0
T1	236258	248	0	0
T2	8841	2	0	0
T3	3445	4	0	0
T4	3665	4	0	0
T5	5829	0	0	0
T6	4167	10	0	0
T7	8367	1	0	0
T8	11267	5	0	0
T9	1649	1	0	0
T10	1602	0	0	0
T11	0	75	0	0
T25	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	1139	0	0
T1	236258	34	0	0
T2	8841	2	0	0
T3	3445	0	0	0
T4	3665	0	0	0
T5	5829	0	0	0
T6	4167	0	0	0
T7	8367	1	0	0
T8	11267	5	0	0
T9	1649	0	0	0
T10	1602	0	0	0
T14	0	23	0	0
T15	0	4	0	0
T25	0	5	0	0
T28	0	15	0	0
T30	0	12	0	0
T40	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54787928	13062	0	0
T1	945017	224	0	0
T2	35371	9	0	0
T3	13792	4	0	0
T4	14672	4	0	0
T5	23332	0	0	0
T6	16668	9	0	0
T7	33474	2	0	0
T8	45071	6	0	0
T9	6597	1	0	0
T10	6413	0	0	0
T11	0	65	0	0
T25	0	7	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54787928	1130	0	0
T1	945017	34	0	0
T2	35371	9	0	0
T3	13792	0	0	0
T4	14672	0	0	0
T5	23332	0	0	0
T6	16668	0	0	0
T7	33474	2	0	0
T8	45071	6	0	0
T9	6597	0	0	0
T10	6413	0	0	0
T14	0	24	0	0
T25	0	7	0	0
T26	0	2	0	0
T28	0	14	0	0
T30	0	11	0	0
T40	0	7	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54787928	13062	0	0
T1	945017	224	0	0
T2	35371	9	0	0
T3	13792	4	0	0
T4	14672	4	0	0
T5	23332	0	0	0
T6	16668	9	0	0
T7	33474	2	0	0
T8	45071	6	0	0
T9	6597	1	0	0
T10	6413	0	0	0
T11	0	65	0	0
T25	0	7	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54787928	1130	0	0
T1	945017	34	0	0
T2	35371	9	0	0
T3	13792	0	0	0
T4	14672	0	0	0
T5	23332	0	0	0
T6	16668	0	0	0
T7	33474	2	0	0
T8	45071	6	0	0
T9	6597	0	0	0
T10	6413	0	0	0
T14	0	24	0	0
T25	0	7	0	0
T26	0	2	0	0
T28	0	14	0	0
T30	0	11	0	0
T40	0	7	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394874	13069	0	0
T1	472500	227	0	0
T2	17685	8	0	0
T3	6895	4	0	0
T4	7336	4	0	0
T5	11665	0	0	0
T6	8334	9	0	0
T7	16737	3	0	0
T8	22535	6	0	0
T9	3298	1	0	0
T10	3206	0	0	0
T11	0	65	0	0
T25	0	7	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394874	1081	0	0
T1	472500	35	0	0
T2	17685	8	0	0
T3	6895	0	0	0
T4	7336	0	0	0
T5	11665	0	0	0
T6	8334	0	0	0
T7	16737	3	0	0
T8	22535	6	0	0
T9	3298	0	0	0
T10	3206	0	0	0
T14	0	23	0	0
T25	0	7	0	0
T26	0	3	0	0
T28	0	13	0	0
T30	0	12	0	0
T40	0	6	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394874	13069	0	0
T1	472500	227	0	0
T2	17685	8	0	0
T3	6895	4	0	0
T4	7336	4	0	0
T5	11665	0	0	0
T6	8334	9	0	0
T7	16737	3	0	0
T8	22535	6	0	0
T9	3298	1	0	0
T10	3206	0	0	0
T11	0	65	0	0
T25	0	7	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394874	1081	0	0
T1	472500	35	0	0
T2	17685	8	0	0
T3	6895	0	0	0
T4	7336	0	0	0
T5	11665	0	0	0
T6	8334	0	0	0
T7	16737	3	0	0
T8	22535	6	0	0
T9	3298	0	0	0
T10	3206	0	0	0
T14	0	23	0	0
T25	0	7	0	0
T26	0	3	0	0
T28	0	13	0	0
T30	0	12	0	0
T40	0	6	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394695	13166	0	0
T1	472520	227	0	0
T2	17685	10	0	0
T3	6897	4	0	0
T4	7333	4	0	0
T5	11658	0	0	0
T6	8334	9	0	0
T7	16737	4	0	0
T8	22536	8	0	0
T9	3297	1	0	0
T10	3206	0	0	0
T11	0	65	0	0
T25	0	8	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394695	1172	0	0
T1	472520	36	0	0
T2	17685	10	0	0
T3	6897	0	0	0
T4	7333	0	0	0
T5	11658	0	0	0
T6	8334	0	0	0
T7	16737	4	0	0
T8	22536	8	0	0
T9	3297	0	0	0
T10	3206	0	0	0
T14	0	23	0	0
T25	0	8	0	0
T26	0	3	0	0
T28	0	15	0	0
T30	0	10	0	0
T40	0	6	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394695	13166	0	0
T1	472520	227	0	0
T2	17685	10	0	0
T3	6897	4	0	0
T4	7333	4	0	0
T5	11658	0	0	0
T6	8334	9	0	0
T7	16737	4	0	0
T8	22536	8	0	0
T9	3297	1	0	0
T10	3206	0	0	0
T11	0	65	0	0
T25	0	8	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27394695	1172	0	0
T1	472520	36	0	0
T2	17685	10	0	0
T3	6897	0	0	0
T4	7333	0	0	0
T5	11658	0	0	0
T6	8334	0	0	0
T7	16737	4	0	0
T8	22536	8	0	0
T9	3297	0	0	0
T10	3206	0	0	0
T14	0	23	0	0
T25	0	8	0	0
T26	0	3	0	0
T28	0	15	0	0
T30	0	10	0	0
T40	0	6	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1729518	22199	0	0
T1	29936	369	0	0
T2	1105	13	0	0
T3	429	6	0	0
T4	458	5	0	0
T5	730	2	0	0
T6	519	11	0	0
T7	1045	6	0	0
T8	1407	10	0	0
T9	205	2	0	0
T10	199	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1729518	1196	0	0
T1	29936	38	0	0
T2	1105	12	0	0
T3	429	0	0	0
T4	458	0	0	0
T5	730	0	0	0
T6	519	0	0	0
T7	1045	5	0	0
T8	1407	9	0	0
T9	205	0	0	0
T10	199	0	0	0
T14	0	25	0	0
T25	0	10	0	0
T26	0	5	0	0
T28	0	19	0	0
T30	0	9	0	0
T40	0	5	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1729518	22199	0	0
T1	29936	369	0	0
T2	1105	13	0	0
T3	429	6	0	0
T4	458	5	0	0
T5	730	2	0	0
T6	519	11	0	0
T7	1045	6	0	0
T8	1407	10	0	0
T9	205	2	0	0
T10	199	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1729518	1196	0	0
T1	29936	38	0	0
T2	1105	12	0	0
T3	429	0	0	0
T4	458	0	0	0
T5	730	0	0	0
T6	519	0	0	0
T7	1045	5	0	0
T8	1407	9	0	0
T9	205	0	0	0
T10	199	0	0	0
T14	0	25	0	0
T25	0	10	0	0
T26	0	5	0	0
T28	0	19	0	0
T30	0	9	0	0
T40	0	5	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	14602	0	0
T1	236258	250	0	0
T2	8841	13	0	0
T3	3445	4	0	0
T4	3665	4	0	0
T5	5829	0	0	0
T6	4167	10	0	0
T7	8367	6	0	0
T8	11267	10	0	0
T9	1649	1	0	0
T10	1602	0	0	0
T11	0	75	0	0
T25	0	10	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	1289	0	0
T1	236258	37	0	0
T2	8841	13	0	0
T3	3445	0	0	0
T4	3665	0	0	0
T5	5829	0	0	0
T6	4167	0	0	0
T7	8367	6	0	0
T8	11267	10	0	0
T9	1649	0	0	0
T10	1602	0	0	0
T14	0	26	0	0
T25	0	10	0	0
T26	0	5	0	0
T28	0	16	0	0
T30	0	11	0	0
T40	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	14602	0	0
T1	236258	250	0	0
T2	8841	13	0	0
T3	3445	4	0	0
T4	3665	4	0	0
T5	5829	0	0	0
T6	4167	10	0	0
T7	8367	6	0	0
T8	11267	10	0	0
T9	1649	1	0	0
T10	1602	0	0	0
T11	0	75	0	0
T25	0	10	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	1289	0	0
T1	236258	37	0	0
T2	8841	13	0	0
T3	3445	0	0	0
T4	3665	0	0	0
T5	5829	0	0	0
T6	4167	0	0	0
T7	8367	6	0	0
T8	11267	10	0	0
T9	1649	0	0	0
T10	1602	0	0	0
T14	0	26	0	0
T25	0	10	0	0
T26	0	5	0	0
T28	0	16	0	0
T30	0	11	0	0
T40	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	14624	0	0
T1	236258	252	0	0
T2	8841	12	0	0
T3	3445	4	0	0
T4	3665	4	0	0
T5	5829	0	0	0
T6	4167	10	0	0
T7	8367	7	0	0
T8	11267	12	0	0
T9	1649	1	0	0
T10	1602	0	0	0
T11	0	75	0	0
T25	0	12	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	1299	0	0
T1	236258	37	0	0
T2	8841	12	0	0
T3	3445	0	0	0
T4	3665	0	0	0
T5	5829	0	0	0
T6	4167	0	0	0
T7	8367	7	0	0
T8	11267	12	0	0
T9	1649	0	0	0
T10	1602	0	0	0
T14	0	28	0	0
T25	0	12	0	0
T26	0	6	0	0
T28	0	12	0	0
T30	0	11	0	0
T40	0	7	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	14624	0	0
T1	236258	252	0	0
T2	8841	12	0	0
T3	3445	4	0	0
T4	3665	4	0	0
T5	5829	0	0	0
T6	4167	10	0	0
T7	8367	7	0	0
T8	11267	12	0	0
T9	1649	1	0	0
T10	1602	0	0	0
T11	0	75	0	0
T25	0	12	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	1299	0	0
T1	236258	37	0	0
T2	8841	12	0	0
T3	3445	0	0	0
T4	3665	0	0	0
T5	5829	0	0	0
T6	4167	0	0	0
T7	8367	7	0	0
T8	11267	12	0	0
T9	1649	0	0	0
T10	1602	0	0	0
T14	0	28	0	0
T25	0	12	0	0
T26	0	6	0	0
T28	0	12	0	0
T30	0	11	0	0
T40	0	7	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	14681	0	0
T1	236258	251	0	0
T2	8841	14	0	0
T3	3445	4	0	0
T4	3665	4	0	0
T5	5829	0	0	0
T6	4167	10	0	0
T7	8367	7	0	0
T8	11267	11	0	0
T9	1649	1	0	0
T10	1602	0	0	0
T11	0	75	0	0
T25	0	14	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	1358	0	0
T1	236258	36	0	0
T2	8841	14	0	0
T3	3445	0	0	0
T4	3665	0	0	0
T5	5829	0	0	0
T6	4167	0	0	0
T7	8367	7	0	0
T8	11267	11	0	0
T9	1649	0	0	0
T10	1602	0	0	0
T14	0	27	0	0
T25	0	14	0	0
T26	0	8	0	0
T28	0	15	0	0
T30	0	6	0	0
T40	0	7	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	14681	0	0
T1	236258	251	0	0
T2	8841	14	0	0
T3	3445	4	0	0
T4	3665	4	0	0
T5	5829	0	0	0
T6	4167	10	0	0
T7	8367	7	0	0
T8	11267	11	0	0
T9	1649	1	0	0
T10	1602	0	0	0
T11	0	75	0	0
T25	0	14	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13696907	1358	0	0
T1	236258	36	0	0
T2	8841	14	0	0
T3	3445	0	0	0
T4	3665	0	0	0
T5	5829	0	0	0
T6	4167	0	0	0
T7	8367	7	0	0
T8	11267	11	0	0
T9	1649	0	0	0
T10	1602	0	0	0
T14	0	27	0	0
T25	0	14	0	0
T26	0	8	0	0
T28	0	15	0	0
T30	0	6	0	0
T40	0	7	0	0