Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12883855	8784	0	0
alert_regwen_rd_A	12883855	5790	0	0
cpu_regwen_rd_A	12883855	5846	0	0
sw_rst_ctrl_n_0_rd_A	12883855	10713	0	0
sw_rst_ctrl_n_1_rd_A	12883855	10586	0	0
sw_rst_ctrl_n_2_rd_A	12883855	10323	0	0
sw_rst_ctrl_n_3_rd_A	12883855	10490	0	0
sw_rst_ctrl_n_4_rd_A	12883855	10455	0	0
sw_rst_ctrl_n_5_rd_A	12883855	10633	0	0
sw_rst_ctrl_n_6_rd_A	12883855	10588	0	0
sw_rst_ctrl_n_7_rd_A	12883855	10881	0	0
sw_rst_regwen_0_rd_A	12883855	6430	0	0
sw_rst_regwen_1_rd_A	12883855	6490	0	0
sw_rst_regwen_2_rd_A	12883855	6537	0	0
sw_rst_regwen_3_rd_A	12883855	6523	0	0
sw_rst_regwen_4_rd_A	12883855	6609	0	0
sw_rst_regwen_5_rd_A	12883855	6617	0	0
sw_rst_regwen_6_rd_A	12883855	6566	0	0
sw_rst_regwen_7_rd_A	12883855	6508	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	8784	0	0
T60	2634	59	0	0
T61	21900	2	0	0
T63	11111	622	0	0
T64	2896	12	0	0
T81	4557	805	0	0
T82	4335	198	0	0
T83	21902	1	0	0
T84	4659	129	0	0
T87	10438	2	0	0
T88	9813	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	5790	0	0
T28	271123	418	0	0
T29	3701	0	0	0
T30	13229	0	0	0
T40	52175	46	0	0
T41	1741	0	0	0
T78	0	24	0	0
T79	0	246	0	0
T80	5281	0	0	0
T91	0	70	0	0
T92	0	278	0	0
T95	0	77	0	0
T96	1503	0	0	0
T97	1898	0	0	0
T98	3707	0	0	0
T99	1744	0	0	0
T101	0	115	0	0
T102	0	207	0	0
T125	0	59	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	5846	0	0
T28	271123	393	0	0
T29	3701	0	0	0
T30	13229	0	0	0
T40	52175	46	0	0
T41	1741	0	0	0
T78	0	18	0	0
T79	0	226	0	0
T80	5281	0	0	0
T91	0	47	0	0
T92	0	325	0	0
T95	0	84	0	0
T96	1503	0	0	0
T97	1898	0	0	0
T98	3707	0	0	0
T99	1744	0	0	0
T101	0	100	0	0
T102	0	215	0	0
T125	0	57	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	10713	0	0
T6	3448	32	0	0
T7	8349	139	0	0
T8	11249	166	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T28	0	661	0	0
T30	0	155	0	0
T40	0	118	0	0
T59	1629	0	0	0
T78	0	20	0	0
T79	0	324	0	0
T91	0	52	0	0
T98	0	24	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	10586	0	0
T6	3448	35	0	0
T7	8349	112	0	0
T8	11249	176	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T28	0	617	0	0
T30	0	143	0	0
T40	0	130	0	0
T59	1629	0	0	0
T78	0	22	0	0
T79	0	298	0	0
T97	0	1	0	0
T98	0	29	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	10323	0	0
T6	3448	20	0	0
T7	8349	129	0	0
T8	11249	175	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T28	0	655	0	0
T30	0	146	0	0
T40	0	93	0	0
T59	1629	0	0	0
T78	0	15	0	0
T79	0	307	0	0
T97	0	1	0	0
T98	0	41	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	10490	0	0
T6	3448	32	0	0
T7	8349	140	0	0
T8	11249	144	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T28	0	655	0	0
T30	0	157	0	0
T40	0	153	0	0
T59	1629	0	0	0
T78	0	20	0	0
T79	0	334	0	0
T97	0	11	0	0
T98	0	26	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	10455	0	0
T6	3448	40	0	0
T7	8349	117	0	0
T8	11249	172	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T28	0	681	0	0
T30	0	127	0	0
T40	0	117	0	0
T59	1629	0	0	0
T78	0	43	0	0
T79	0	309	0	0
T97	0	8	0	0
T98	0	14	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	10633	0	0
T6	3448	36	0	0
T7	8349	83	0	0
T8	11249	150	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T28	0	608	0	0
T30	0	154	0	0
T40	0	142	0	0
T59	1629	0	0	0
T78	0	22	0	0
T79	0	372	0	0
T97	0	2	0	0
T98	0	21	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	10588	0	0
T6	3448	41	0	0
T7	8349	133	0	0
T8	11249	174	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T28	0	676	0	0
T30	0	174	0	0
T40	0	147	0	0
T59	1629	0	0	0
T78	0	22	0	0
T79	0	324	0	0
T97	0	4	0	0
T98	0	16	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	10881	0	0
T6	3448	17	0	0
T7	8349	111	0	0
T8	11249	165	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T28	0	706	0	0
T30	0	147	0	0
T40	0	147	0	0
T59	1629	0	0	0
T78	0	10	0	0
T79	0	275	0	0
T91	0	77	0	0
T98	0	34	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	6430	0	0
T7	8349	34	0	0
T8	11249	10	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T26	2709	0	0	0
T28	0	393	0	0
T40	0	58	0	0
T59	1629	0	0	0
T78	0	23	0	0
T79	0	227	0	0
T91	0	59	0	0
T92	0	326	0	0
T95	0	74	0	0
T126	0	2	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	6490	0	0
T7	8349	27	0	0
T8	11249	31	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T26	2709	0	0	0
T28	0	440	0	0
T40	0	38	0	0
T59	1629	0	0	0
T78	0	42	0	0
T79	0	197	0	0
T91	0	30	0	0
T92	0	322	0	0
T95	0	98	0	0
T126	0	3	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	6537	0	0
T7	8349	36	0	0
T8	11249	40	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T26	2709	0	0	0
T28	0	424	0	0
T40	0	60	0	0
T59	1629	0	0	0
T78	0	28	0	0
T79	0	276	0	0
T91	0	60	0	0
T92	0	349	0	0
T95	0	113	0	0
T126	0	11	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	6523	0	0
T7	8349	30	0	0
T8	11249	34	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T26	2709	0	0	0
T28	0	457	0	0
T40	0	82	0	0
T59	1629	0	0	0
T78	0	24	0	0
T79	0	252	0	0
T91	0	67	0	0
T92	0	276	0	0
T95	0	90	0	0
T126	0	3	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	6609	0	0
T7	8349	27	0	0
T8	11249	26	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T26	2709	0	0	0
T28	0	404	0	0
T40	0	54	0	0
T59	1629	0	0	0
T78	0	15	0	0
T79	0	242	0	0
T91	0	57	0	0
T92	0	321	0	0
T95	0	83	0	0
T126	0	7	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	6617	0	0
T7	8349	22	0	0
T8	11249	40	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T26	2709	0	0	0
T28	0	432	0	0
T40	0	57	0	0
T59	1629	0	0	0
T78	0	24	0	0
T79	0	233	0	0
T91	0	49	0	0
T92	0	299	0	0
T95	0	113	0	0
T126	0	6	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	6566	0	0
T7	8349	30	0	0
T8	11249	37	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T26	2709	0	0	0
T28	0	336	0	0
T40	0	50	0	0
T59	1629	0	0	0
T78	0	13	0	0
T79	0	253	0	0
T91	0	41	0	0
T92	0	373	0	0
T95	0	88	0	0
T126	0	11	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12883855	6508	0	0
T7	8349	20	0	0
T8	11249	33	0	0
T9	1504	0	0	0
T10	1512	0	0	0
T11	42051	0	0	0
T12	4920	0	0	0
T13	53519	0	0	0
T25	3308	0	0	0
T26	2709	0	0	0
T28	0	395	0	0
T40	0	52	0	0
T59	1629	0	0	0
T78	0	17	0	0
T79	0	218	0	0
T91	0	68	0	0
T92	0	307	0	0
T95	0	82	0	0
T126	0	8	0	0