Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	604214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

366356

1

T2

7076

T3

64

T4

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	516365	1			T2	10796		T3	99		T5	99
values[0x0]	226511	1			T2	4253		T3	55		T4	8
values[0x1]	227694	1			T2	4266		T3	58		T4	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	507951	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

462619

1

T2

9035

T3

80

T4

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3491	1			T2	88		T3	2		T6	6
valid_sources[0x01]	4244	1			T2	89		T3	1		T6	1
valid_sources[0x02]	3102	1			T2	60		T3	2		T6	3
valid_sources[0x03]	3265	1			T2	62		T3	2		T6	3
valid_sources[0x04]	4066	1			T2	64		T6	3		T12	31
valid_sources[0x05]	3353	1			T2	58		T6	3		T10	366
valid_sources[0x06]	2714	1			T2	59		T6	3		T12	23
valid_sources[0x07]	3265	1			T2	59		T3	4		T6	5
valid_sources[0x08]	3256	1			T2	77		T3	1		T6	5
valid_sources[0x09]	3392	1			T2	59		T11	17		T12	16
valid_sources[0x0a]	3743	1			T2	86		T6	5		T10	283
valid_sources[0x0b]	3907	1			T2	68		T6	4		T9	1
valid_sources[0x0c]	3836	1			T2	70		T3	2		T6	3
valid_sources[0x0d]	3650	1			T2	78		T6	5		T12	8
valid_sources[0x0e]	3428	1			T2	54		T6	5		T10	197
valid_sources[0x0f]	4499	1			T2	77		T6	4		T12	70
valid_sources[0x10]	3092	1			T2	67		T3	1		T6	2
valid_sources[0x11]	3661	1			T2	60		T3	3		T6	5
valid_sources[0x12]	3182	1			T2	77		T6	2		T11	21
valid_sources[0x13]	3793	1			T2	74		T6	7		T11	52
valid_sources[0x14]	6741	1			T2	88		T6	4		T9	1
valid_sources[0x15]	3188	1			T2	88		T6	4		T11	7
valid_sources[0x16]	3530	1			T2	75		T6	2		T11	25
valid_sources[0x17]	6313	1			T2	102		T3	1		T6	4
valid_sources[0x18]	6561	1			T2	81		T3	1		T6	5
valid_sources[0x19]	2961	1			T2	72		T3	2		T6	2
valid_sources[0x1a]	4081	1			T2	87		T3	1		T6	1
valid_sources[0x1b]	2910	1			T2	73		T6	3		T10	70
valid_sources[0x1c]	3370	1			T2	72		T3	1		T6	2
valid_sources[0x1d]	2884	1			T2	88		T6	1		T12	14
valid_sources[0x1e]	3314	1			T2	72		T3	2		T6	2
valid_sources[0x1f]	4493	1			T2	85		T3	2		T6	3
valid_sources[0x20]	3101	1			T2	58		T6	2		T10	55
valid_sources[0x21]	3178	1			T2	84		T6	4		T10	70
valid_sources[0x22]	6831	1			T2	97		T3	2		T6	3
valid_sources[0x23]	3149	1			T2	88		T6	4		T11	18
valid_sources[0x24]	7315	1			T2	94		T6	10		T12	3
valid_sources[0x25]	2993	1			T2	84		T3	2		T6	1
valid_sources[0x26]	3024	1			T2	78		T3	2		T6	7
valid_sources[0x27]	3502	1			T2	82		T6	6		T12	61
valid_sources[0x28]	3509	1			T2	110		T3	1		T6	4
valid_sources[0x29]	4118	1			T2	66		T6	5		T12	71
valid_sources[0x2a]	3439	1			T2	55		T6	3		T10	112
valid_sources[0x2b]	3318	1			T2	71		T3	2		T10	211
valid_sources[0x2c]	3963	1			T2	60		T6	2		T11	34
valid_sources[0x2d]	3869	1			T2	101		T6	1		T10	13
valid_sources[0x2e]	2989	1			T2	75		T3	1		T6	5
valid_sources[0x2f]	4204	1			T2	63		T3	1		T6	3
valid_sources[0x30]	3367	1			T2	92		T3	1		T10	198
valid_sources[0x31]	2919	1			T2	65		T3	1		T11	17
valid_sources[0x32]	3341	1			T2	60		T6	4		T11	36
valid_sources[0x33]	3822	1			T2	67		T3	1		T6	3
valid_sources[0x34]	3358	1			T2	92		T3	1		T6	5
valid_sources[0x35]	4681	1			T2	77		T3	3		T6	2
valid_sources[0x36]	2912	1			T2	54		T3	1		T10	113
valid_sources[0x37]	3166	1			T2	91		T3	1		T6	3
valid_sources[0x38]	3080	1			T2	61		T6	3		T12	29
valid_sources[0x39]	3439	1			T2	81		T3	1		T6	3
valid_sources[0x3a]	3262	1			T2	83		T6	3		T11	46
valid_sources[0x3b]	3956	1			T2	76		T6	4		T10	70
valid_sources[0x3c]	3294	1			T2	61		T3	2		T6	8
valid_sources[0x3d]	3200	1			T2	104		T3	1		T6	4
valid_sources[0x3e]	3128	1			T2	53		T3	1		T6	6
valid_sources[0x3f]	3504	1			T2	60		T11	19		T12	49
valid_sources[0x40]	3502	1			T2	70		T6	4		T12	11
valid_sources[0x41]	3411	1			T2	53		T3	3		T6	4
valid_sources[0x42]	3262	1			T2	79		T3	1		T6	5
valid_sources[0x43]	3138	1			T2	69		T6	1		T11	22
valid_sources[0x44]	3948	1			T2	91		T3	2		T6	3
valid_sources[0x45]	3386	1			T2	74		T3	2		T6	3
valid_sources[0x46]	3791	1			T2	73		T6	3		T12	5
valid_sources[0x47]	3826	1			T2	50		T6	8		T12	50
valid_sources[0x48]	3976	1			T2	91		T3	1		T6	3
valid_sources[0x49]	3210	1			T2	71		T6	3		T12	19
valid_sources[0x4a]	3627	1			T2	87		T6	9		T10	112
valid_sources[0x4b]	3305	1			T2	65		T6	3		T12	55
valid_sources[0x4c]	3850	1			T2	53		T6	3		T10	65
valid_sources[0x4d]	3947	1			T2	85		T6	5		T10	494
valid_sources[0x4e]	4356	1			T2	98		T3	1		T6	3
valid_sources[0x4f]	3715	1			T2	48		T3	1		T6	6
valid_sources[0x50]	3309	1			T2	59		T3	1		T6	3
valid_sources[0x51]	3156	1			T2	101		T3	2		T6	8
valid_sources[0x52]	3220	1			T2	98		T6	4		T10	70
valid_sources[0x53]	3290	1			T2	79		T3	2		T6	4
valid_sources[0x54]	3002	1			T2	82		T12	18		T33	28
valid_sources[0x55]	4190	1			T2	89		T3	2		T6	2
valid_sources[0x56]	4859	1			T2	70		T3	3		T6	2
valid_sources[0x57]	3007	1			T2	101		T3	2		T6	2
valid_sources[0x58]	4396	1			T2	82		T3	1		T10	195
valid_sources[0x59]	4240	1			T2	65		T3	2		T6	3
valid_sources[0x5a]	3470	1			T2	97		T3	3		T6	4
valid_sources[0x5b]	3183	1			T2	65		T6	4		T10	66
valid_sources[0x5c]	3184	1			T2	46		T3	2		T6	5
valid_sources[0x5d]	4138	1			T2	79		T6	5		T10	155
valid_sources[0x5e]	3437	1			T2	72		T6	3		T11	62
valid_sources[0x5f]	4267	1			T2	79		T9	1		T11	2
valid_sources[0x60]	3250	1			T2	53		T6	9		T12	56
valid_sources[0x61]	3896	1			T2	113		T3	1		T6	6
valid_sources[0x62]	3035	1			T2	77		T3	1		T11	45
valid_sources[0x63]	3401	1			T2	62		T3	3		T6	7
valid_sources[0x64]	3155	1			T2	68		T6	5		T10	151
valid_sources[0x65]	3301	1			T2	75		T3	1		T6	2
valid_sources[0x66]	3138	1			T2	83		T3	3		T6	4
valid_sources[0x67]	3676	1			T2	43		T6	3		T10	233
valid_sources[0x68]	3216	1			T2	68		T3	1		T6	1
valid_sources[0x69]	4094	1			T2	64		T6	3		T11	41
valid_sources[0x6a]	3267	1			T2	89		T3	1		T6	2
valid_sources[0x6b]	3310	1			T2	61		T6	2		T12	37
valid_sources[0x6c]	3425	1			T2	85		T3	1		T6	1
valid_sources[0x6d]	3684	1			T2	93		T3	2		T6	5
valid_sources[0x6e]	3589	1			T2	86		T6	3		T11	2
valid_sources[0x6f]	3385	1			T2	81		T3	1		T6	4
valid_sources[0x70]	4736	1			T2	78		T3	2		T6	4
valid_sources[0x71]	3207	1			T2	58		T6	4		T11	9
valid_sources[0x72]	7283	1			T2	65		T11	5		T12	6
valid_sources[0x73]	3855	1			T2	75		T3	2		T6	4
valid_sources[0x74]	3082	1			T2	96		T3	3		T6	1
valid_sources[0x75]	4065	1			T2	78		T3	1		T6	8
valid_sources[0x76]	3728	1			T2	67		T3	1		T10	396
valid_sources[0x77]	3148	1			T2	85		T3	3		T6	5
valid_sources[0x78]	3185	1			T2	80		T12	19		T13	1
valid_sources[0x79]	4119	1			T2	73		T6	3		T12	21
valid_sources[0x7a]	4395	1			T2	96		T3	2		T6	3
valid_sources[0x7b]	3462	1			T2	81		T3	1		T6	4
valid_sources[0x7c]	3045	1			T2	87		T3	1		T6	3
valid_sources[0x7d]	2890	1			T2	85		T3	1		T6	13
valid_sources[0x7e]	4064	1			T2	55		T3	1		T6	3
valid_sources[0x7f]	3237	1			T2	99		T3	1		T6	3
valid_sources[0x80]	6633	1			T2	68		T3	3		T11	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

243441

1

T2

5043

T3

36

T5

49

values[0x0]

all_enables

biggest_size

79591

1

T2

1354

T3

20

T4

4

values[0x1]

all_enables

biggest_size

43324

1

T2

679

T3

8

T5

7