Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T5,T10
1	0	Covered	T2,T10,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52353729	8232	0	0
CascadeEffAonToRstPorAboveRise_A	52353729	8232	0	0
CascadeEffAonToRstPorIoAboveFall_A	50257672	8232	0	0
CascadeEffAonToRstPorIoAboveRise_A	50257672	8232	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25129804	8232	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25129804	8232	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12564673	8232	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12564673	8232	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25129729	8232	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25129729	8232	0	0
CascadeLcToLcAboveFall_A	52353729	21012	0	0
CascadeLcToLcAboveRise_A	52353729	21012	0	0
CascadeLcToLcAonAboveFall_A	1586715	21012	0	0
CascadeLcToLcAonAboveRise_A	1586715	21012	0	0
CascadeLcToLcShadowedAboveFall_A	52353729	21012	0	0
CascadeLcToLcShadowedAboveRise_A	52353729	21012	0	0
CascadePorToAonAboveFall_A	1586715	6421	0	0
CascadeSysToSysAboveFall_A	52353729	21012	0	0
CascadeSysToSysAboveRise_A	52353729	21012	0	0
ScanRstToAonRise_A	1586715	217	0	0
StablePorToAonRise_A	1586715	8232	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11161925	21012	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11161925	21012	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11161925	21012	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11161925	21012	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12564673	21012	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12564673	21012	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11161925	21012	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11161925	21012	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11161925	21012	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11161925	21012	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52353729	8232	0	0
T1	24253	8	0	0
T2	652363	140	0	0
T3	9858	2	0	0
T4	7914	1	0	0
T5	10689	2	0	0
T6	34113	1	0	0
T7	11287	1	0	0
T8	24389	8	0	0
T9	6183	1	0	0
T10	959817	124	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52353729	8232	0	0
T1	24253	8	0	0
T2	652363	140	0	0
T3	9858	2	0	0
T4	7914	1	0	0
T5	10689	2	0	0
T6	34113	1	0	0
T7	11287	1	0	0
T8	24389	8	0	0
T9	6183	1	0	0
T10	959817	124	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50257672	8232	0	0
T1	23285	8	0	0
T2	626279	140	0	0
T3	9459	2	0	0
T4	7596	1	0	0
T5	10268	2	0	0
T6	32747	1	0	0
T7	10836	1	0	0
T8	23426	8	0	0
T9	5937	1	0	0
T10	921386	124	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50257672	8232	0	0
T1	23285	8	0	0
T2	626279	140	0	0
T3	9459	2	0	0
T4	7596	1	0	0
T5	10268	2	0	0
T6	32747	1	0	0
T7	10836	1	0	0
T8	23426	8	0	0
T9	5937	1	0	0
T10	921386	124	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129804	8232	0	0
T1	11647	8	0	0
T2	313151	140	0	0
T3	4729	2	0	0
T4	3798	1	0	0
T5	5132	2	0	0
T6	16374	1	0	0
T7	5417	1	0	0
T8	11709	8	0	0
T9	2966	1	0	0
T10	460722	124	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129804	8232	0	0
T1	11647	8	0	0
T2	313151	140	0	0
T3	4729	2	0	0
T4	3798	1	0	0
T5	5132	2	0	0
T6	16374	1	0	0
T7	5417	1	0	0
T8	11709	8	0	0
T9	2966	1	0	0
T10	460722	124	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	8232	0	0
T1	5816	8	0	0
T2	156546	140	0	0
T3	2364	2	0	0
T4	1899	1	0	0
T5	2564	2	0	0
T6	8185	1	0	0
T7	2708	1	0	0
T8	5853	8	0	0
T9	1482	1	0	0
T10	230356	124	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	8232	0	0
T1	5816	8	0	0
T2	156546	140	0	0
T3	2364	2	0	0
T4	1899	1	0	0
T5	2564	2	0	0
T6	8185	1	0	0
T7	2708	1	0	0
T8	5853	8	0	0
T9	1482	1	0	0
T10	230356	124	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129729	8232	0	0
T1	11643	8	0	0
T2	313118	140	0	0
T3	4729	2	0	0
T4	3798	1	0	0
T5	5133	2	0	0
T6	16374	1	0	0
T7	5417	1	0	0
T8	11697	8	0	0
T9	2967	1	0	0
T10	460727	124	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129729	8232	0	0
T1	11643	8	0	0
T2	313118	140	0	0
T3	4729	2	0	0
T4	3798	1	0	0
T5	5133	2	0	0
T6	16374	1	0	0
T7	5417	1	0	0
T8	11697	8	0	0
T9	2967	1	0	0
T10	460727	124	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52353729	21012	0	0
T1	24253	8	0	0
T2	652363	355	0	0
T3	9858	6	0	0
T4	7914	1	0	0
T5	10689	6	0	0
T6	34113	1	0	0
T7	11287	10	0	0
T8	24389	8	0	0
T9	6183	1	0	0
T10	959817	359	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52353729	21012	0	0
T1	24253	8	0	0
T2	652363	355	0	0
T3	9858	6	0	0
T4	7914	1	0	0
T5	10689	6	0	0
T6	34113	1	0	0
T7	11287	10	0	0
T8	24389	8	0	0
T9	6183	1	0	0
T10	959817	359	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1586715	21012	0	0
T1	729	8	0	0
T2	19945	355	0	0
T3	295	6	0	0
T4	236	1	0	0
T5	319	6	0	0
T6	1021	1	0	0
T7	337	10	0	0
T8	733	8	0	0
T9	184	1	0	0
T10	29174	359	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1586715	21012	0	0
T1	729	8	0	0
T2	19945	355	0	0
T3	295	6	0	0
T4	236	1	0	0
T5	319	6	0	0
T6	1021	1	0	0
T7	337	10	0	0
T8	733	8	0	0
T9	184	1	0	0
T10	29174	359	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52353729	21012	0	0
T1	24253	8	0	0
T2	652363	355	0	0
T3	9858	6	0	0
T4	7914	1	0	0
T5	10689	6	0	0
T6	34113	1	0	0
T7	11287	10	0	0
T8	24389	8	0	0
T9	6183	1	0	0
T10	959817	359	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52353729	21012	0	0
T1	24253	8	0	0
T2	652363	355	0	0
T3	9858	6	0	0
T4	7914	1	0	0
T5	10689	6	0	0
T6	34113	1	0	0
T7	11287	10	0	0
T8	24389	8	0	0
T9	6183	1	0	0
T10	959817	359	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1586715	6421	0	0
T1	729	8	0	0
T2	19945	85	0	0
T3	295	1	0	0
T4	236	1	0	0
T5	319	1	0	0
T6	1021	1	0	0
T7	337	1	0	0
T8	733	8	0	0
T9	184	1	0	0
T10	29174	68	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52353729	21012	0	0
T1	24253	8	0	0
T2	652363	355	0	0
T3	9858	6	0	0
T4	7914	1	0	0
T5	10689	6	0	0
T6	34113	1	0	0
T7	11287	10	0	0
T8	24389	8	0	0
T9	6183	1	0	0
T10	959817	359	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52353729	21012	0	0
T1	24253	8	0	0
T2	652363	355	0	0
T3	9858	6	0	0
T4	7914	1	0	0
T5	10689	6	0	0
T6	34113	1	0	0
T7	11287	10	0	0
T8	24389	8	0	0
T9	6183	1	0	0
T10	959817	359	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1586715	217	0	0
T2	19945	4	0	0
T3	295	0	0	0
T4	236	0	0	0
T5	319	0	0	0
T6	1021	0	0	0
T7	337	0	0	0
T8	733	0	0	0
T9	184	0	0	0
T10	29174	5	0	0
T11	7073	0	0	0
T12	0	1	0	0
T13	0	1	0	0
T26	0	3	0	0
T28	0	6	0	0
T30	0	2	0	0
T77	0	3	0	0
T83	0	3	0	0
T92	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1586715	8232	0	0
T1	729	8	0	0
T2	19945	140	0	0
T3	295	2	0	0
T4	236	1	0	0
T5	319	2	0	0
T6	1021	1	0	0
T7	337	1	0	0
T8	733	8	0	0
T9	184	1	0	0
T10	29174	124	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11161925	21012	0	0
T1	5659	8	0	0
T2	126807	355	0	0
T3	2176	6	0	0
T4	1880	1	0	0
T5	2324	6	0	0
T6	8096	1	0	0
T7	2065	10	0	0
T8	5117	8	0	0
T9	1441	1	0	0
T10	198700	359	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11161925	21012	0	0
T1	5659	8	0	0
T2	126807	355	0	0
T3	2176	6	0	0
T4	1880	1	0	0
T5	2324	6	0	0
T6	8096	1	0	0
T7	2065	10	0	0
T8	5117	8	0	0
T9	1441	1	0	0
T10	198700	359	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11161925	21012	0	0
T1	5659	8	0	0
T2	126807	355	0	0
T3	2176	6	0	0
T4	1880	1	0	0
T5	2324	6	0	0
T6	8096	1	0	0
T7	2065	10	0	0
T8	5117	8	0	0
T9	1441	1	0	0
T10	198700	359	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11161925	21012	0	0
T1	5659	8	0	0
T2	126807	355	0	0
T3	2176	6	0	0
T4	1880	1	0	0
T5	2324	6	0	0
T6	8096	1	0	0
T7	2065	10	0	0
T8	5117	8	0	0
T9	1441	1	0	0
T10	198700	359	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	21012	0	0
T1	5816	8	0	0
T2	156546	355	0	0
T3	2364	6	0	0
T4	1899	1	0	0
T5	2564	6	0	0
T6	8185	1	0	0
T7	2708	10	0	0
T8	5853	8	0	0
T9	1482	1	0	0
T10	230356	359	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	21012	0	0
T1	5816	8	0	0
T2	156546	355	0	0
T3	2364	6	0	0
T4	1899	1	0	0
T5	2564	6	0	0
T6	8185	1	0	0
T7	2708	10	0	0
T8	5853	8	0	0
T9	1482	1	0	0
T10	230356	359	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11161925	21012	0	0
T1	5659	8	0	0
T2	126807	355	0	0
T3	2176	6	0	0
T4	1880	1	0	0
T5	2324	6	0	0
T6	8096	1	0	0
T7	2065	10	0	0
T8	5117	8	0	0
T9	1441	1	0	0
T10	198700	359	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11161925	21012	0	0
T1	5659	8	0	0
T2	126807	355	0	0
T3	2176	6	0	0
T4	1880	1	0	0
T5	2324	6	0	0
T6	8096	1	0	0
T7	2065	10	0	0
T8	5117	8	0	0
T9	1441	1	0	0
T10	198700	359	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11161925	21012	0	0
T1	5659	8	0	0
T2	126807	355	0	0
T3	2176	6	0	0
T4	1880	1	0	0
T5	2324	6	0	0
T6	8096	1	0	0
T7	2065	10	0	0
T8	5117	8	0	0
T9	1441	1	0	0
T10	198700	359	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11161925	21012	0	0
T1	5659	8	0	0
T2	126807	355	0	0
T3	2176	6	0	0
T4	1880	1	0	0
T5	2324	6	0	0
T6	8096	1	0	0
T7	2065	10	0	0
T8	5117	8	0	0
T9	1441	1	0	0
T10	198700	359	0	0