Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T10
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12564673	13692	0	0
gen_assertions[0].RstEnOn_A	12564673	1072	0	0
gen_assertions[0].RstNOff_A	12564673	13692	0	0
gen_assertions[0].RstNOn_A	12564673	1072	0	0
gen_assertions[1].RstEnOff_A	50257672	12370	0	0
gen_assertions[1].RstEnOn_A	50257672	1069	0	0
gen_assertions[1].RstNOff_A	50257672	12370	0	0
gen_assertions[1].RstNOn_A	50257672	1069	0	0
gen_assertions[2].RstEnOff_A	25129804	12390	0	0
gen_assertions[2].RstEnOn_A	25129804	1019	0	0
gen_assertions[2].RstNOff_A	25129804	12390	0	0
gen_assertions[2].RstNOn_A	25129804	1019	0	0
gen_assertions[3].RstEnOff_A	25129729	12470	0	0
gen_assertions[3].RstEnOn_A	25129729	1091	0	0
gen_assertions[3].RstNOff_A	25129729	12470	0	0
gen_assertions[3].RstNOn_A	25129729	1091	0	0
gen_assertions[4].RstEnOff_A	1586715	20834	0	0
gen_assertions[4].RstEnOn_A	1586715	1124	0	0
gen_assertions[4].RstNOff_A	1586715	20834	0	0
gen_assertions[4].RstNOn_A	1586715	1124	0	0
gen_assertions[5].RstEnOff_A	12564673	13923	0	0
gen_assertions[5].RstEnOn_A	12564673	1183	0	0
gen_assertions[5].RstNOff_A	12564673	13923	0	0
gen_assertions[5].RstNOn_A	12564673	1183	0	0
gen_assertions[6].RstEnOff_A	12564673	13973	0	0
gen_assertions[6].RstEnOn_A	12564673	1228	0	0
gen_assertions[6].RstNOff_A	12564673	13973	0	0
gen_assertions[6].RstNOn_A	12564673	1228	0	0
gen_assertions[7].RstEnOff_A	12564673	14019	0	0
gen_assertions[7].RstEnOn_A	12564673	1274	0	0
gen_assertions[7].RstNOff_A	12564673	14019	0	0
gen_assertions[7].RstNOn_A	12564673	1274	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	13692	0	0
T2	156546	240	0	0
T3	2364	4	0	0
T4	1899	0	0	0
T5	2564	4	0	0
T6	8185	3	0	0
T7	2708	9	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	241	0	0
T11	56469	75	0	0
T12	0	124	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	1072	0	0
T2	156546	28	0	0
T3	2364	0	0	0
T4	1899	0	0	0
T5	2564	0	0	0
T6	8185	3	0	0
T7	2708	4	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	7	0	0
T11	56469	0	0	0
T12	0	29	0	0
T15	0	3	0	0
T27	0	34	0	0
T28	0	21	0	0
T29	0	5	0	0
T31	0	18	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	13692	0	0
T2	156546	240	0	0
T3	2364	4	0	0
T4	1899	0	0	0
T5	2564	4	0	0
T6	8185	3	0	0
T7	2708	9	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	241	0	0
T11	56469	75	0	0
T12	0	124	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	1072	0	0
T2	156546	28	0	0
T3	2364	0	0	0
T4	1899	0	0	0
T5	2564	0	0	0
T6	8185	3	0	0
T7	2708	4	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	7	0	0
T11	56469	0	0	0
T12	0	29	0	0
T15	0	3	0	0
T27	0	34	0	0
T28	0	21	0	0
T29	0	5	0	0
T31	0	18	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50257672	12370	0	0
T2	626279	216	0	0
T3	9459	3	0	0
T4	7596	0	0	0
T5	10268	4	0	0
T6	32747	5	0	0
T7	10836	9	0	0
T8	23426	0	0	0
T9	5937	0	0	0
T10	921386	213	0	0
T11	225867	66	0	0
T12	0	111	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50257672	1069	0	0
T2	626279	28	0	0
T3	9459	0	0	0
T4	7596	0	0	0
T5	10268	0	0	0
T6	32747	5	0	0
T7	10836	3	0	0
T8	23426	0	0	0
T9	5937	0	0	0
T10	921386	7	0	0
T11	225867	0	0	0
T12	0	27	0	0
T15	0	2	0	0
T27	0	38	0	0
T28	0	27	0	0
T29	0	7	0	0
T31	0	15	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50257672	12370	0	0
T2	626279	216	0	0
T3	9459	3	0	0
T4	7596	0	0	0
T5	10268	4	0	0
T6	32747	5	0	0
T7	10836	9	0	0
T8	23426	0	0	0
T9	5937	0	0	0
T10	921386	213	0	0
T11	225867	66	0	0
T12	0	111	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50257672	1069	0	0
T2	626279	28	0	0
T3	9459	0	0	0
T4	7596	0	0	0
T5	10268	0	0	0
T6	32747	5	0	0
T7	10836	3	0	0
T8	23426	0	0	0
T9	5937	0	0	0
T10	921386	7	0	0
T11	225867	0	0	0
T12	0	27	0	0
T15	0	2	0	0
T27	0	38	0	0
T28	0	27	0	0
T29	0	7	0	0
T31	0	15	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129804	12390	0	0
T2	313151	216	0	0
T3	4729	3	0	0
T4	3798	0	0	0
T5	5132	4	0	0
T6	16374	6	0	0
T7	5417	9	0	0
T8	11709	0	0	0
T9	2966	0	0	0
T10	460722	213	0	0
T11	112917	66	0	0
T12	0	103	0	0
T13	0	5	0	0
T14	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129804	1019	0	0
T2	313151	26	0	0
T3	4729	0	0	0
T4	3798	0	0	0
T5	5132	0	0	0
T6	16374	6	0	0
T7	5417	1	0	0
T8	11709	0	0	0
T9	2966	0	0	0
T10	460722	7	0	0
T11	112917	0	0	0
T12	0	19	0	0
T13	0	1	0	0
T27	0	28	0	0
T28	0	26	0	0
T29	0	7	0	0
T31	0	16	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129804	12390	0	0
T2	313151	216	0	0
T3	4729	3	0	0
T4	3798	0	0	0
T5	5132	4	0	0
T6	16374	6	0	0
T7	5417	9	0	0
T8	11709	0	0	0
T9	2966	0	0	0
T10	460722	213	0	0
T11	112917	66	0	0
T12	0	103	0	0
T13	0	5	0	0
T14	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129804	1019	0	0
T2	313151	26	0	0
T3	4729	0	0	0
T4	3798	0	0	0
T5	5132	0	0	0
T6	16374	6	0	0
T7	5417	1	0	0
T8	11709	0	0	0
T9	2966	0	0	0
T10	460722	7	0	0
T11	112917	0	0	0
T12	0	19	0	0
T13	0	1	0	0
T27	0	28	0	0
T28	0	26	0	0
T29	0	7	0	0
T31	0	16	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129729	12470	0	0
T2	313118	218	0	0
T3	4729	3	0	0
T4	3798	0	0	0
T5	5133	4	0	0
T6	16374	5	0	0
T7	5417	9	0	0
T8	11697	0	0	0
T9	2967	0	0	0
T10	460727	214	0	0
T11	112923	66	0	0
T12	0	108	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129729	1091	0	0
T2	313118	30	0	0
T3	4729	0	0	0
T4	3798	0	0	0
T5	5133	0	0	0
T6	16374	5	0	0
T7	5417	0	0	0
T8	11697	0	0	0
T9	2967	0	0	0
T10	460727	8	0	0
T11	112923	0	0	0
T12	0	25	0	0
T27	0	33	0	0
T28	0	21	0	0
T29	0	7	0	0
T31	0	17	0	0
T61	0	5	0	0
T83	0	27	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129729	12470	0	0
T2	313118	218	0	0
T3	4729	3	0	0
T4	3798	0	0	0
T5	5133	4	0	0
T6	16374	5	0	0
T7	5417	9	0	0
T8	11697	0	0	0
T9	2967	0	0	0
T10	460727	214	0	0
T11	112923	66	0	0
T12	0	108	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25129729	1091	0	0
T2	313118	30	0	0
T3	4729	0	0	0
T4	3798	0	0	0
T5	5133	0	0	0
T6	16374	5	0	0
T7	5417	0	0	0
T8	11697	0	0	0
T9	2967	0	0	0
T10	460727	8	0	0
T11	112923	0	0	0
T12	0	25	0	0
T27	0	33	0	0
T28	0	21	0	0
T29	0	7	0	0
T31	0	17	0	0
T61	0	5	0	0
T83	0	27	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1586715	20834	0	0
T1	729	2	0	0
T2	19945	369	0	0
T3	295	5	0	0
T4	236	1	0	0
T5	319	5	0	0
T6	1021	10	0	0
T7	337	9	0	0
T8	733	2	0	0
T9	184	1	0	0
T10	29174	361	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1586715	1124	0	0
T2	19945	27	0	0
T3	295	0	0	0
T4	236	0	0	0
T5	319	0	0	0
T6	1021	9	0	0
T7	337	0	0	0
T8	733	0	0	0
T9	184	0	0	0
T10	29174	5	0	0
T11	7073	0	0	0
T12	0	28	0	0
T13	0	1	0	0
T27	0	34	0	0
T28	0	18	0	0
T29	0	10	0	0
T31	0	14	0	0
T83	0	22	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1586715	20834	0	0
T1	729	2	0	0
T2	19945	369	0	0
T3	295	5	0	0
T4	236	1	0	0
T5	319	5	0	0
T6	1021	10	0	0
T7	337	9	0	0
T8	733	2	0	0
T9	184	1	0	0
T10	29174	361	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1586715	1124	0	0
T2	19945	27	0	0
T3	295	0	0	0
T4	236	0	0	0
T5	319	0	0	0
T6	1021	9	0	0
T7	337	0	0	0
T8	733	0	0	0
T9	184	0	0	0
T10	29174	5	0	0
T11	7073	0	0	0
T12	0	28	0	0
T13	0	1	0	0
T27	0	34	0	0
T28	0	18	0	0
T29	0	10	0	0
T31	0	14	0	0
T83	0	22	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	13923	0	0
T2	156546	240	0	0
T3	2364	4	0	0
T4	1899	0	0	0
T5	2564	4	0	0
T6	8185	10	0	0
T7	2708	9	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	239	0	0
T11	56469	75	0	0
T12	0	118	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	1183	0	0
T2	156546	28	0	0
T3	2364	0	0	0
T4	1899	0	0	0
T5	2564	0	0	0
T6	8185	10	0	0
T7	2708	0	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	4	0	0
T11	56469	0	0	0
T12	0	24	0	0
T27	0	30	0	0
T28	0	24	0	0
T29	0	10	0	0
T31	0	17	0	0
T61	0	7	0	0
T83	0	24	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	13923	0	0
T2	156546	240	0	0
T3	2364	4	0	0
T4	1899	0	0	0
T5	2564	4	0	0
T6	8185	10	0	0
T7	2708	9	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	239	0	0
T11	56469	75	0	0
T12	0	118	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	1183	0	0
T2	156546	28	0	0
T3	2364	0	0	0
T4	1899	0	0	0
T5	2564	0	0	0
T6	8185	10	0	0
T7	2708	0	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	4	0	0
T11	56469	0	0	0
T12	0	24	0	0
T27	0	30	0	0
T28	0	24	0	0
T29	0	10	0	0
T31	0	17	0	0
T61	0	7	0	0
T83	0	24	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	13973	0	0
T2	156546	243	0	0
T3	2364	4	0	0
T4	1899	0	0	0
T5	2564	4	0	0
T6	8185	11	0	0
T7	2708	9	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	241	0	0
T11	56469	75	0	0
T12	0	123	0	0
T13	0	5	0	0
T14	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	1228	0	0
T2	156546	31	0	0
T3	2364	0	0	0
T4	1899	0	0	0
T5	2564	0	0	0
T6	8185	11	0	0
T7	2708	0	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	6	0	0
T11	56469	0	0	0
T12	0	28	0	0
T13	0	1	0	0
T27	0	39	0	0
T28	0	21	0	0
T29	0	12	0	0
T31	0	15	0	0
T83	0	26	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	13973	0	0
T2	156546	243	0	0
T3	2364	4	0	0
T4	1899	0	0	0
T5	2564	4	0	0
T6	8185	11	0	0
T7	2708	9	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	241	0	0
T11	56469	75	0	0
T12	0	123	0	0
T13	0	5	0	0
T14	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	1228	0	0
T2	156546	31	0	0
T3	2364	0	0	0
T4	1899	0	0	0
T5	2564	0	0	0
T6	8185	11	0	0
T7	2708	0	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	6	0	0
T11	56469	0	0	0
T12	0	28	0	0
T13	0	1	0	0
T27	0	39	0	0
T28	0	21	0	0
T29	0	12	0	0
T31	0	15	0	0
T83	0	26	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	14019	0	0
T2	156546	244	0	0
T3	2364	4	0	0
T4	1899	0	0	0
T5	2564	4	0	0
T6	8185	10	0	0
T7	2708	9	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	240	0	0
T11	56469	75	0	0
T12	0	124	0	0
T13	0	5	0	0
T14	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	1274	0	0
T2	156546	31	0	0
T3	2364	0	0	0
T4	1899	0	0	0
T5	2564	0	0	0
T6	8185	10	0	0
T7	2708	0	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	5	0	0
T11	56469	0	0	0
T12	0	30	0	0
T13	0	1	0	0
T27	0	31	0	0
T28	0	20	0	0
T29	0	13	0	0
T31	0	16	0	0
T83	0	27	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	14019	0	0
T2	156546	244	0	0
T3	2364	4	0	0
T4	1899	0	0	0
T5	2564	4	0	0
T6	8185	10	0	0
T7	2708	9	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	240	0	0
T11	56469	75	0	0
T12	0	124	0	0
T13	0	5	0	0
T14	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12564673	1274	0	0
T2	156546	31	0	0
T3	2364	0	0	0
T4	1899	0	0	0
T5	2564	0	0	0
T6	8185	10	0	0
T7	2708	0	0	0
T8	5853	0	0	0
T9	1482	0	0	0
T10	230356	5	0	0
T11	56469	0	0	0
T12	0	30	0	0
T13	0	1	0	0
T27	0	31	0	0
T28	0	20	0	0
T29	0	13	0	0
T31	0	16	0	0
T83	0	27	0	0