Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12020664	9159	0	0
alert_regwen_rd_A	12020664	6712	0	0
cpu_regwen_rd_A	12020664	6390	0	0
sw_rst_ctrl_n_0_rd_A	12020664	11566	0	0
sw_rst_ctrl_n_1_rd_A	12020664	11289	0	0
sw_rst_ctrl_n_2_rd_A	12020664	11170	0	0
sw_rst_ctrl_n_3_rd_A	12020664	11151	0	0
sw_rst_ctrl_n_4_rd_A	12020664	10960	0	0
sw_rst_ctrl_n_5_rd_A	12020664	11245	0	0
sw_rst_ctrl_n_6_rd_A	12020664	11222	0	0
sw_rst_ctrl_n_7_rd_A	12020664	11101	0	0
sw_rst_regwen_0_rd_A	12020664	7088	0	0
sw_rst_regwen_1_rd_A	12020664	6943	0	0
sw_rst_regwen_2_rd_A	12020664	6879	0	0
sw_rst_regwen_3_rd_A	12020664	7040	0	0
sw_rst_regwen_4_rd_A	12020664	6950	0	0
sw_rst_regwen_5_rd_A	12020664	6937	0	0
sw_rst_regwen_6_rd_A	12020664	7138	0	0
sw_rst_regwen_7_rd_A	12020664	7125	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	9159	0	0
T63	3871	12	0	0
T64	2541	14	0	0
T65	20085	3	0	0
T68	4206	726	0	0
T69	11830	437	0	0
T84	4507	16	0	0
T85	2527	5	0	0
T86	19928	3	0	0
T87	2794	83	0	0
T88	3925	114	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	6712	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	77	0	0
T31	17731	0	0	0
T32	1248	0	0	0
T67	2655	0	0	0
T75	0	67	0	0
T83	71944	0	0	0
T94	0	56	0	0
T96	0	553	0	0
T97	0	413	0	0
T119	0	137	0	0
T120	0	55	0	0
T121	0	49	0	0
T122	0	37	0	0
T123	0	294	0	0
T124	5484	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	6390	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	67	0	0
T31	17731	0	0	0
T32	1248	0	0	0
T67	2655	0	0	0
T75	0	55	0	0
T83	71944	0	0	0
T94	0	45	0	0
T96	0	581	0	0
T97	0	373	0	0
T119	0	107	0	0
T120	0	47	0	0
T121	0	53	0	0
T122	0	66	0	0
T123	0	301	0	0
T124	5484	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	11566	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	56	0	0
T31	17731	211	0	0
T32	1248	0	0	0
T56	0	126	0	0
T67	2655	0	0	0
T75	0	73	0	0
T78	0	84	0	0
T80	0	116	0	0
T81	0	139	0	0
T83	71944	0	0	0
T94	0	45	0	0
T124	5484	88	0	0
T125	0	22	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	11289	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	56	0	0
T31	17731	180	0	0
T32	1248	0	0	0
T56	0	96	0	0
T67	2655	0	0	0
T75	0	76	0	0
T78	0	89	0	0
T80	0	120	0	0
T81	0	178	0	0
T83	71944	0	0	0
T94	0	37	0	0
T124	5484	64	0	0
T125	0	10	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	11170	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	54	0	0
T31	17731	201	0	0
T32	1248	0	0	0
T56	0	127	0	0
T67	2655	0	0	0
T75	0	91	0	0
T78	0	115	0	0
T80	0	146	0	0
T81	0	159	0	0
T83	71944	0	0	0
T94	0	63	0	0
T119	0	556	0	0
T124	5484	60	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	11151	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	57	0	0
T31	17731	231	0	0
T32	1248	0	0	0
T56	0	131	0	0
T67	2655	0	0	0
T75	0	110	0	0
T78	0	87	0	0
T80	0	118	0	0
T81	0	151	0	0
T83	71944	0	0	0
T94	0	54	0	0
T124	5484	87	0	0
T125	0	10	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	10960	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	98	0	0
T31	17731	194	0	0
T32	1248	0	0	0
T56	0	57	0	0
T67	2655	0	0	0
T75	0	61	0	0
T78	0	80	0	0
T80	0	123	0	0
T81	0	154	0	0
T83	71944	0	0	0
T94	0	32	0	0
T124	5484	65	0	0
T125	0	3	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	11245	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	72	0	0
T31	17731	205	0	0
T32	1248	0	0	0
T56	0	73	0	0
T67	2655	0	0	0
T75	0	78	0	0
T78	0	65	0	0
T80	0	102	0	0
T81	0	141	0	0
T83	71944	0	0	0
T94	0	65	0	0
T119	0	637	0	0
T124	5484	70	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	11222	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	62	0	0
T31	17731	231	0	0
T32	1248	0	0	0
T56	0	108	0	0
T67	2655	0	0	0
T75	0	95	0	0
T78	0	109	0	0
T80	0	79	0	0
T81	0	169	0	0
T83	71944	0	0	0
T94	0	67	0	0
T124	5484	81	0	0
T125	0	7	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	11101	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	65	0	0
T31	17731	259	0	0
T32	1248	0	0	0
T56	0	99	0	0
T67	2655	0	0	0
T75	0	59	0	0
T78	0	112	0	0
T80	0	133	0	0
T81	0	154	0	0
T83	71944	0	0	0
T94	0	74	0	0
T124	5484	69	0	0
T125	0	10	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	7088	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	71	0	0
T31	17731	0	0	0
T32	1248	0	0	0
T56	0	27	0	0
T67	2655	0	0	0
T75	0	62	0	0
T78	0	35	0	0
T80	0	27	0	0
T81	0	27	0	0
T83	71944	0	0	0
T94	0	57	0	0
T119	0	78	0	0
T124	5484	0	0	0
T126	0	23	0	0
T127	0	40	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	6943	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	86	0	0
T31	17731	0	0	0
T32	1248	0	0	0
T56	0	14	0	0
T67	2655	0	0	0
T75	0	92	0	0
T78	0	33	0	0
T80	0	44	0	0
T81	0	37	0	0
T83	71944	0	0	0
T94	0	41	0	0
T119	0	97	0	0
T124	5484	0	0	0
T125	0	7	0	0
T128	0	12	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	6879	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	49	0	0
T31	17731	0	0	0
T32	1248	0	0	0
T56	0	19	0	0
T67	2655	0	0	0
T75	0	80	0	0
T78	0	14	0	0
T80	0	40	0	0
T81	0	27	0	0
T83	71944	0	0	0
T94	0	56	0	0
T119	0	120	0	0
T124	5484	0	0	0
T126	0	17	0	0
T128	0	7	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	7040	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	62	0	0
T31	17731	0	0	0
T32	1248	0	0	0
T56	0	17	0	0
T67	2655	0	0	0
T75	0	69	0	0
T78	0	18	0	0
T80	0	39	0	0
T81	0	23	0	0
T83	71944	0	0	0
T94	0	64	0	0
T119	0	100	0	0
T124	5484	0	0	0
T125	0	1	0	0
T128	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	6950	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	63	0	0
T31	17731	0	0	0
T32	1248	0	0	0
T56	0	30	0	0
T67	2655	0	0	0
T75	0	65	0	0
T78	0	18	0	0
T80	0	27	0	0
T81	0	35	0	0
T83	71944	0	0	0
T94	0	49	0	0
T119	0	98	0	0
T124	5484	0	0	0
T125	0	4	0	0
T128	0	3	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	6937	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	61	0	0
T31	17731	0	0	0
T32	1248	0	0	0
T56	0	32	0	0
T67	2655	0	0	0
T75	0	74	0	0
T78	0	9	0	0
T80	0	41	0	0
T81	0	39	0	0
T83	71944	0	0	0
T94	0	59	0	0
T119	0	117	0	0
T124	5484	0	0	0
T125	0	6	0	0
T128	0	2	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	7138	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	69	0	0
T31	17731	0	0	0
T32	1248	0	0	0
T56	0	30	0	0
T67	2655	0	0	0
T75	0	62	0	0
T78	0	26	0	0
T80	0	35	0	0
T81	0	50	0	0
T83	71944	0	0	0
T94	0	53	0	0
T119	0	88	0	0
T124	5484	0	0	0
T125	0	1	0	0
T128	0	13	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12020664	7125	0	0
T18	2856	0	0	0
T19	2812	0	0	0
T20	2410	0	0	0
T21	2485	0	0	0
T30	41439	61	0	0
T31	17731	0	0	0
T32	1248	0	0	0
T56	0	9	0	0
T67	2655	0	0	0
T75	0	78	0	0
T80	0	27	0	0
T81	0	23	0	0
T83	71944	0	0	0
T94	0	63	0	0
T119	0	120	0	0
T124	5484	0	0	0
T125	0	8	0	0
T126	0	13	0	0
T128	0	9	0	0