Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	650104	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

391353

1

T1

1103

T2

397

T4

263

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	556210	1			T1	1500		T2	547		T3	10
values[0x0]	242085	1			T1	816		T2	243		T4	181
values[0x1]	243162	1			T1	884		T2	258		T4	168

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	545374	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

496083

1

T1

1470

T2

490

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3839	1			T1	13		T9	1		T13	4
valid_sources[0x01]	4806	1			T1	5		T4	744		T9	3
valid_sources[0x02]	4231	1			T1	18		T9	3		T13	4
valid_sources[0x03]	5953	1			T1	12		T13	8		T14	13
valid_sources[0x04]	3678	1			T1	14		T9	3		T13	6
valid_sources[0x05]	3017	1			T1	4		T9	2		T13	3
valid_sources[0x06]	7025	1			T1	15		T9	1		T13	2
valid_sources[0x07]	3230	1			T1	11		T9	3		T13	2
valid_sources[0x08]	3297	1			T1	6		T9	2		T13	3
valid_sources[0x09]	3436	1			T1	6		T9	4		T13	5
valid_sources[0x0a]	3750	1			T1	8		T9	2		T13	4
valid_sources[0x0b]	3582	1			T1	7		T9	2		T13	8
valid_sources[0x0c]	3723	1			T1	9		T9	2		T13	6
valid_sources[0x0d]	4305	1			T1	14		T9	5		T13	6
valid_sources[0x0e]	3477	1			T1	17		T9	7		T13	7
valid_sources[0x0f]	4269	1			T1	21		T9	3		T13	4
valid_sources[0x10]	3710	1			T1	15		T9	4		T13	4
valid_sources[0x11]	3934	1			T1	20		T9	8		T13	4
valid_sources[0x12]	4329	1			T1	2		T9	1		T13	3
valid_sources[0x13]	3422	1			T1	16		T9	3		T13	6
valid_sources[0x14]	3674	1			T1	15		T9	2		T13	3
valid_sources[0x15]	3790	1			T1	11		T9	1		T13	2
valid_sources[0x16]	3721	1			T1	24		T9	1		T13	3
valid_sources[0x17]	3682	1			T1	2		T9	4		T13	4
valid_sources[0x18]	3021	1			T1	15		T13	3		T14	7
valid_sources[0x19]	4578	1			T1	9		T9	2		T13	3
valid_sources[0x1a]	4438	1			T1	23		T9	3		T13	6
valid_sources[0x1b]	3276	1			T1	1		T13	1		T14	10
valid_sources[0x1c]	4472	1			T1	17		T13	2		T14	14
valid_sources[0x1d]	3498	1			T1	8		T9	2		T13	4
valid_sources[0x1e]	3588	1			T1	15		T9	5		T13	4
valid_sources[0x1f]	3523	1			T1	12		T9	5		T12	1
valid_sources[0x20]	3842	1			T1	13		T9	3		T13	9
valid_sources[0x21]	3426	1			T1	6		T9	3		T13	2
valid_sources[0x22]	4352	1			T1	6		T13	1		T14	15
valid_sources[0x23]	4793	1			T1	4		T9	1		T13	5
valid_sources[0x24]	2934	1			T1	24		T9	3		T13	4
valid_sources[0x25]	3325	1			T1	9		T9	1		T13	4
valid_sources[0x26]	3958	1			T1	9		T9	1		T13	5
valid_sources[0x27]	3585	1			T1	11		T9	2		T13	6
valid_sources[0x28]	3806	1			T1	5		T9	2		T13	6
valid_sources[0x29]	3990	1			T1	23		T9	5		T13	7
valid_sources[0x2a]	7204	1			T1	16		T9	2		T13	6
valid_sources[0x2b]	3775	1			T1	13		T9	3		T13	1
valid_sources[0x2c]	4211	1			T1	28		T9	5		T13	9
valid_sources[0x2d]	8061	1			T1	5		T9	2		T14	15
valid_sources[0x2e]	3592	1			T1	18		T9	1		T13	6
valid_sources[0x2f]	3366	1			T1	9		T9	5		T14	18
valid_sources[0x30]	3653	1			T1	21		T9	2		T13	7
valid_sources[0x31]	4297	1			T1	20		T9	5		T13	8
valid_sources[0x32]	3662	1			T1	7		T9	2		T13	3
valid_sources[0x33]	4137	1			T1	5		T9	6		T13	3
valid_sources[0x34]	3847	1			T1	16		T9	2		T13	7
valid_sources[0x35]	3402	1			T1	19		T9	3		T13	2
valid_sources[0x36]	4045	1			T1	19		T9	3		T13	7
valid_sources[0x37]	4551	1			T1	13		T9	1		T13	6
valid_sources[0x38]	3688	1			T1	7		T9	2		T13	2
valid_sources[0x39]	3752	1			T1	7		T9	2		T13	2
valid_sources[0x3a]	3546	1			T1	14		T9	8		T13	3
valid_sources[0x3b]	4114	1			T1	14		T9	2		T13	1
valid_sources[0x3c]	3830	1			T1	9		T9	2		T13	4
valid_sources[0x3d]	4229	1			T1	10		T9	4		T13	1
valid_sources[0x3e]	4374	1			T1	25		T9	6		T13	6
valid_sources[0x3f]	3764	1			T1	9		T9	2		T13	2
valid_sources[0x40]	4616	1			T1	17		T9	4		T13	4
valid_sources[0x41]	3917	1			T1	5		T9	6		T13	5
valid_sources[0x42]	6568	1			T1	21		T9	1		T13	3
valid_sources[0x43]	3831	1			T1	16		T9	4		T13	11
valid_sources[0x44]	3442	1			T1	19		T9	1		T13	1
valid_sources[0x45]	5356	1			T1	9		T9	2		T13	2
valid_sources[0x46]	3475	1			T1	8		T9	2		T13	1
valid_sources[0x47]	3556	1			T1	8		T9	3		T13	10
valid_sources[0x48]	4971	1			T1	10		T9	3		T13	3
valid_sources[0x49]	4002	1			T1	4		T9	4		T13	4
valid_sources[0x4a]	4015	1			T1	17		T9	7		T13	6
valid_sources[0x4b]	3601	1			T1	17		T9	3		T13	9
valid_sources[0x4c]	3655	1			T1	19		T9	4		T13	2
valid_sources[0x4d]	3596	1			T1	12		T9	7		T13	3
valid_sources[0x4e]	3409	1			T1	14		T13	8		T14	7
valid_sources[0x4f]	4086	1			T1	13		T9	5		T13	5
valid_sources[0x50]	6719	1			T1	8		T9	5		T13	2
valid_sources[0x51]	3283	1			T1	16		T6	1		T9	2
valid_sources[0x52]	3685	1			T1	13		T9	4		T13	4
valid_sources[0x53]	3730	1			T1	8		T9	1		T13	2
valid_sources[0x54]	3752	1			T1	18		T9	2		T13	3
valid_sources[0x55]	4823	1			T1	5		T9	6		T13	1
valid_sources[0x56]	3546	1			T1	5		T9	3		T13	2
valid_sources[0x57]	3301	1			T1	13		T9	3		T13	7
valid_sources[0x58]	6964	1			T1	7		T9	7		T13	2
valid_sources[0x59]	4452	1			T1	7		T9	4		T13	5
valid_sources[0x5a]	3807	1			T1	6		T9	2		T13	5
valid_sources[0x5b]	3753	1			T1	23		T9	3		T13	3
valid_sources[0x5c]	3696	1			T1	8		T9	1		T13	6
valid_sources[0x5d]	4092	1			T1	16		T3	1		T9	3
valid_sources[0x5e]	3801	1			T1	24		T9	3		T13	4
valid_sources[0x5f]	3557	1			T1	8		T9	3		T13	3
valid_sources[0x60]	3403	1			T1	10		T9	2		T13	3
valid_sources[0x61]	3565	1			T1	7		T3	2		T9	3
valid_sources[0x62]	3555	1			T1	4		T9	1		T13	2
valid_sources[0x63]	4135	1			T1	17		T9	5		T13	9
valid_sources[0x64]	3260	1			T1	7		T9	5		T13	1
valid_sources[0x65]	3405	1			T1	11		T9	1		T13	3
valid_sources[0x66]	3087	1			T1	13		T9	1		T13	4
valid_sources[0x67]	3280	1			T1	17		T9	3		T13	3
valid_sources[0x68]	3716	1			T1	11		T9	9		T13	2
valid_sources[0x69]	3884	1			T1	24		T9	9		T13	8
valid_sources[0x6a]	4540	1			T1	10		T9	2		T13	6
valid_sources[0x6b]	3798	1			T1	14		T9	1		T13	7
valid_sources[0x6c]	7047	1			T1	13		T13	3		T14	27
valid_sources[0x6d]	3994	1			T1	3		T9	5		T13	5
valid_sources[0x6e]	3318	1			T1	11		T9	2		T13	6
valid_sources[0x6f]	3674	1			T1	22		T9	3		T13	2
valid_sources[0x70]	4078	1			T1	9		T5	379		T9	4
valid_sources[0x71]	3752	1			T1	4		T9	2		T13	4
valid_sources[0x72]	3979	1			T1	8		T9	1		T13	8
valid_sources[0x73]	4161	1			T1	8		T9	3		T13	4
valid_sources[0x74]	4709	1			T1	14		T9	2		T13	4
valid_sources[0x75]	4981	1			T1	22		T9	2		T13	2
valid_sources[0x76]	3436	1			T1	32		T9	1		T13	8
valid_sources[0x77]	4287	1			T1	7		T13	4		T14	14
valid_sources[0x78]	4593	1			T1	9		T9	1		T13	4
valid_sources[0x79]	4447	1			T1	13		T9	2		T13	1
valid_sources[0x7a]	4079	1			T1	10		T9	2		T13	4
valid_sources[0x7b]	4317	1			T1	6		T3	1		T9	3
valid_sources[0x7c]	3845	1			T1	4		T9	5		T13	1
valid_sources[0x7d]	3954	1			T1	14		T9	3		T13	2
valid_sources[0x7e]	3765	1			T1	5		T9	3		T13	9
valid_sources[0x7f]	3694	1			T1	24		T13	10		T14	17
valid_sources[0x80]	3211	1			T1	8		T9	2		T13	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

260822

1

T1

687

T2

269

T4

187

values[0x0]

all_enables

biggest_size

84724

1

T1

282

T2

78

T4

52

values[0x1]

all_enables

biggest_size

45807

1

T1

134

T2

50

T4

24