Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T14,T15
0	1	Covered	T5,T14,T15
1	0	Covered	T14,T15,T17

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T5,T14,T15
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54131430	8682	0	0
CascadeEffAonToRstPorAboveRise_A	54131430	8682	0	0
CascadeEffAonToRstPorIoAboveFall_A	51964507	8682	0	0
CascadeEffAonToRstPorIoAboveRise_A	51964507	8682	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25983002	8682	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25983002	8682	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12991121	8682	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12991121	8682	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25982987	8682	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25982987	8682	0	0
CascadeLcToLcAboveFall_A	54131430	22440	0	0
CascadeLcToLcAboveRise_A	54131430	22440	0	0
CascadeLcToLcAonAboveFall_A	1641819	22440	0	0
CascadeLcToLcAonAboveRise_A	1641819	22440	0	0
CascadeLcToLcShadowedAboveFall_A	54131430	22440	0	0
CascadeLcToLcShadowedAboveRise_A	54131430	22440	0	0
CascadePorToAonAboveFall_A	1641819	6732	0	0
CascadeSysToSysAboveFall_A	54131430	22440	0	0
CascadeSysToSysAboveRise_A	54131430	22440	0	0
ScanRstToAonRise_A	1641819	222	0	0
StablePorToAonRise_A	1641819	8682	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11458663	22440	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11458663	22440	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11458663	22440	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11458663	22440	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12991121	22440	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12991121	22440	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11458663	22440	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11458663	22440	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11458663	22440	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11458663	22440	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54131430	8682	0	0
T1	235621	27	0	0
T2	46011	1	0	0
T3	831898	271	0	0
T4	33338	1	0	0
T5	10731	2	0	0
T6	12272	2	0	0
T7	24271	8	0	0
T8	24343	8	0	0
T9	26897	1	0	0
T10	14136	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54131430	8682	0	0
T1	235621	27	0	0
T2	46011	1	0	0
T3	831898	271	0	0
T4	33338	1	0	0
T5	10731	2	0	0
T6	12272	2	0	0
T7	24271	8	0	0
T8	24343	8	0	0
T9	26897	1	0	0
T10	14136	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51964507	8682	0	0
T1	226213	27	0	0
T2	44169	1	0	0
T3	798644	271	0	0
T4	32003	1	0	0
T5	10302	2	0	0
T6	11781	2	0	0
T7	23304	8	0	0
T8	23371	8	0	0
T9	25820	1	0	0
T10	13570	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51964507	8682	0	0
T1	226213	27	0	0
T2	44169	1	0	0
T3	798644	271	0	0
T4	32003	1	0	0
T5	10302	2	0	0
T6	11781	2	0	0
T7	23304	8	0	0
T8	23371	8	0	0
T9	25820	1	0	0
T10	13570	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25983002	8682	0	0
T1	113102	27	0	0
T2	22084	1	0	0
T3	399346	271	0	0
T4	16002	1	0	0
T5	5150	2	0	0
T6	5890	2	0	0
T7	11660	8	0	0
T8	11684	8	0	0
T9	12910	1	0	0
T10	6785	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25983002	8682	0	0
T1	113102	27	0	0
T2	22084	1	0	0
T3	399346	271	0	0
T4	16002	1	0	0
T5	5150	2	0	0
T6	5890	2	0	0
T7	11660	8	0	0
T8	11684	8	0	0
T9	12910	1	0	0
T10	6785	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	8682	0	0
T1	56550	27	0	0
T2	11041	1	0	0
T3	199632	271	0	0
T4	8000	1	0	0
T5	2575	2	0	0
T6	2944	2	0	0
T7	5823	8	0	0
T8	5839	8	0	0
T9	6454	1	0	0
T10	3392	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	8682	0	0
T1	56550	27	0	0
T2	11041	1	0	0
T3	199632	271	0	0
T4	8000	1	0	0
T5	2575	2	0	0
T6	2944	2	0	0
T7	5823	8	0	0
T8	5839	8	0	0
T9	6454	1	0	0
T10	3392	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25982987	8682	0	0
T1	113099	27	0	0
T2	22084	1	0	0
T3	399345	271	0	0
T4	16002	1	0	0
T5	5152	2	0	0
T6	5890	2	0	0
T7	11657	8	0	0
T8	11682	8	0	0
T9	12909	1	0	0
T10	6785	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25982987	8682	0	0
T1	113099	27	0	0
T2	22084	1	0	0
T3	399345	271	0	0
T4	16002	1	0	0
T5	5152	2	0	0
T6	5890	2	0	0
T7	11657	8	0	0
T8	11682	8	0	0
T9	12909	1	0	0
T10	6785	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54131430	22440	0	0
T1	235621	102	0	0
T2	46011	1	0	0
T3	831898	271	0	0
T4	33338	1	0	0
T5	10731	6	0	0
T6	12272	2	0	0
T7	24271	8	0	0
T8	24343	8	0	0
T9	26897	1	0	0
T10	14136	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54131430	22440	0	0
T1	235621	102	0	0
T2	46011	1	0	0
T3	831898	271	0	0
T4	33338	1	0	0
T5	10731	6	0	0
T6	12272	2	0	0
T7	24271	8	0	0
T8	24343	8	0	0
T9	26897	1	0	0
T10	14136	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641819	22440	0	0
T1	7083	102	0	0
T2	1378	1	0	0
T3	25079	271	0	0
T4	998	1	0	0
T5	322	6	0	0
T6	368	2	0	0
T7	729	8	0	0
T8	732	8	0	0
T9	805	1	0	0
T10	423	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641819	22440	0	0
T1	7083	102	0	0
T2	1378	1	0	0
T3	25079	271	0	0
T4	998	1	0	0
T5	322	6	0	0
T6	368	2	0	0
T7	729	8	0	0
T8	732	8	0	0
T9	805	1	0	0
T10	423	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54131430	22440	0	0
T1	235621	102	0	0
T2	46011	1	0	0
T3	831898	271	0	0
T4	33338	1	0	0
T5	10731	6	0	0
T6	12272	2	0	0
T7	24271	8	0	0
T8	24343	8	0	0
T9	26897	1	0	0
T10	14136	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54131430	22440	0	0
T1	235621	102	0	0
T2	46011	1	0	0
T3	831898	271	0	0
T4	33338	1	0	0
T5	10731	6	0	0
T6	12272	2	0	0
T7	24271	8	0	0
T8	24343	8	0	0
T9	26897	1	0	0
T10	14136	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641819	6732	0	0
T1	7083	27	0	0
T2	1378	1	0	0
T3	25079	271	0	0
T4	998	1	0	0
T5	322	1	0	0
T6	368	7	0	0
T7	729	8	0	0
T8	732	8	0	0
T9	805	1	0	0
T10	423	11	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54131430	22440	0	0
T1	235621	102	0	0
T2	46011	1	0	0
T3	831898	271	0	0
T4	33338	1	0	0
T5	10731	6	0	0
T6	12272	2	0	0
T7	24271	8	0	0
T8	24343	8	0	0
T9	26897	1	0	0
T10	14136	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54131430	22440	0	0
T1	235621	102	0	0
T2	46011	1	0	0
T3	831898	271	0	0
T4	33338	1	0	0
T5	10731	6	0	0
T6	12272	2	0	0
T7	24271	8	0	0
T8	24343	8	0	0
T9	26897	1	0	0
T10	14136	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641819	222	0	0
T15	12928	1	0	0
T16	661	0	0	0
T17	4821	0	0	0
T26	39818	6	0	0
T27	482	0	0	0
T28	4354	0	0	0
T29	732	0	0	0
T83	1239	0	0	0
T84	914	0	0	0
T85	1201	0	0	0
T93	0	1	0	0
T95	0	5	0	0
T96	0	2	0	0
T98	0	3	0	0
T99	0	1	0	0
T100	0	2	0	0
T121	0	2	0	0
T125	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641819	8682	0	0
T1	7083	27	0	0
T2	1378	1	0	0
T3	25079	271	0	0
T4	998	1	0	0
T5	322	2	0	0
T6	368	2	0	0
T7	729	8	0	0
T8	732	8	0	0
T9	805	1	0	0
T10	423	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11458663	22440	0	0
T1	53372	102	0	0
T2	10975	1	0	0
T3	194151	271	0	0
T4	7981	1	0	0
T5	2476	6	0	0
T6	2782	2	0	0
T7	5090	8	0	0
T8	5488	8	0	0
T9	6364	1	0	0
T10	3349	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11458663	22440	0	0
T1	53372	102	0	0
T2	10975	1	0	0
T3	194151	271	0	0
T4	7981	1	0	0
T5	2476	6	0	0
T6	2782	2	0	0
T7	5090	8	0	0
T8	5488	8	0	0
T9	6364	1	0	0
T10	3349	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11458663	22440	0	0
T1	53372	102	0	0
T2	10975	1	0	0
T3	194151	271	0	0
T4	7981	1	0	0
T5	2476	6	0	0
T6	2782	2	0	0
T7	5090	8	0	0
T8	5488	8	0	0
T9	6364	1	0	0
T10	3349	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11458663	22440	0	0
T1	53372	102	0	0
T2	10975	1	0	0
T3	194151	271	0	0
T4	7981	1	0	0
T5	2476	6	0	0
T6	2782	2	0	0
T7	5090	8	0	0
T8	5488	8	0	0
T9	6364	1	0	0
T10	3349	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	22440	0	0
T1	56550	102	0	0
T2	11041	1	0	0
T3	199632	271	0	0
T4	8000	1	0	0
T5	2575	6	0	0
T6	2944	2	0	0
T7	5823	8	0	0
T8	5839	8	0	0
T9	6454	1	0	0
T10	3392	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	22440	0	0
T1	56550	102	0	0
T2	11041	1	0	0
T3	199632	271	0	0
T4	8000	1	0	0
T5	2575	6	0	0
T6	2944	2	0	0
T7	5823	8	0	0
T8	5839	8	0	0
T9	6454	1	0	0
T10	3392	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11458663	22440	0	0
T1	53372	102	0	0
T2	10975	1	0	0
T3	194151	271	0	0
T4	7981	1	0	0
T5	2476	6	0	0
T6	2782	2	0	0
T7	5090	8	0	0
T8	5488	8	0	0
T9	6364	1	0	0
T10	3349	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11458663	22440	0	0
T1	53372	102	0	0
T2	10975	1	0	0
T3	194151	271	0	0
T4	7981	1	0	0
T5	2476	6	0	0
T6	2782	2	0	0
T7	5090	8	0	0
T8	5488	8	0	0
T9	6364	1	0	0
T10	3349	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11458663	22440	0	0
T1	53372	102	0	0
T2	10975	1	0	0
T3	194151	271	0	0
T4	7981	1	0	0
T5	2476	6	0	0
T6	2782	2	0	0
T7	5090	8	0	0
T8	5488	8	0	0
T9	6364	1	0	0
T10	3349	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11458663	22440	0	0
T1	53372	102	0	0
T2	10975	1	0	0
T3	194151	271	0	0
T4	7981	1	0	0
T5	2476	6	0	0
T6	2782	2	0	0
T7	5090	8	0	0
T8	5488	8	0	0
T9	6364	1	0	0
T10	3349	2	0	0