Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T9
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T9
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T9
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T9
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T9
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T9
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T3,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12991121	14676	0	0
gen_assertions[0].RstEnOn_A	12991121	1069	0	0
gen_assertions[0].RstNOff_A	12991121	14676	0	0
gen_assertions[0].RstNOn_A	12991121	1069	0	0
gen_assertions[1].RstEnOff_A	51964507	13349	0	0
gen_assertions[1].RstEnOn_A	51964507	1053	0	0
gen_assertions[1].RstNOff_A	51964507	13349	0	0
gen_assertions[1].RstNOn_A	51964507	1053	0	0
gen_assertions[2].RstEnOff_A	25983002	13375	0	0
gen_assertions[2].RstEnOn_A	25983002	1044	0	0
gen_assertions[2].RstNOff_A	25983002	13375	0	0
gen_assertions[2].RstNOn_A	25983002	1044	0	0
gen_assertions[3].RstEnOff_A	25982987	13462	0	0
gen_assertions[3].RstEnOn_A	25982987	1124	0	0
gen_assertions[3].RstNOff_A	25982987	13462	0	0
gen_assertions[3].RstNOn_A	25982987	1124	0	0
gen_assertions[4].RstEnOff_A	1641819	22351	0	0
gen_assertions[4].RstEnOn_A	1641819	1141	0	0
gen_assertions[4].RstNOff_A	1641819	22351	0	0
gen_assertions[4].RstNOn_A	1641819	1141	0	0
gen_assertions[5].RstEnOff_A	12991121	14880	0	0
gen_assertions[5].RstEnOn_A	12991121	1164	0	0
gen_assertions[5].RstNOff_A	12991121	14880	0	0
gen_assertions[5].RstNOn_A	12991121	1164	0	0
gen_assertions[6].RstEnOff_A	12991121	14925	0	0
gen_assertions[6].RstEnOn_A	12991121	1205	0	0
gen_assertions[6].RstNOff_A	12991121	14925	0	0
gen_assertions[6].RstNOn_A	12991121	1205	0	0
gen_assertions[7].RstEnOff_A	12991121	15013	0	0
gen_assertions[7].RstEnOn_A	12991121	1294	0	0
gen_assertions[7].RstNOff_A	12991121	15013	0	0
gen_assertions[7].RstNOn_A	12991121	1294	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	14676	0	0
T1	56550	75	0	0
T2	11041	7	0	0
T3	199632	0	0	0
T4	8000	2	0	0
T5	2575	4	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	1	0	0
T10	3392	0	0	0
T11	0	5	0	0
T13	0	9	0	0
T14	0	40	0	0
T15	0	102	0	0
T83	0	3	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	1069	0	0
T2	11041	7	0	0
T3	199632	0	0	0
T4	8000	2	0	0
T5	2575	0	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	1	0	0
T10	3392	0	0	0
T11	0	1	0	0
T13	0	9	0	0
T15	0	5	0	0
T16	0	5	0	0
T18	5836	0	0	0
T26	0	10	0	0
T83	0	3	0	0
T84	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	14676	0	0
T1	56550	75	0	0
T2	11041	7	0	0
T3	199632	0	0	0
T4	8000	2	0	0
T5	2575	4	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	1	0	0
T10	3392	0	0	0
T11	0	5	0	0
T13	0	9	0	0
T14	0	40	0	0
T15	0	102	0	0
T83	0	3	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	1069	0	0
T2	11041	7	0	0
T3	199632	0	0	0
T4	8000	2	0	0
T5	2575	0	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	1	0	0
T10	3392	0	0	0
T11	0	1	0	0
T13	0	9	0	0
T15	0	5	0	0
T16	0	5	0	0
T18	5836	0	0	0
T26	0	10	0	0
T83	0	3	0	0
T84	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51964507	13349	0	0
T1	226213	66	0	0
T2	44169	7	0	0
T3	798644	0	0	0
T4	32003	3	0	0
T5	10302	4	0	0
T6	11781	0	0	0
T7	23304	0	0	0
T8	23371	0	0	0
T9	25820	3	0	0
T10	13570	0	0	0
T11	0	5	0	0
T13	0	8	0	0
T14	0	37	0	0
T15	0	90	0	0
T83	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51964507	1053	0	0
T2	44169	7	0	0
T3	798644	0	0	0
T4	32003	3	0	0
T5	10302	0	0	0
T6	11781	0	0	0
T7	23304	0	0	0
T8	23371	0	0	0
T9	25820	3	0	0
T10	13570	0	0	0
T13	0	8	0	0
T15	0	4	0	0
T18	23337	0	0	0
T26	0	12	0	0
T83	0	4	0	0
T84	0	4	0	0
T85	0	3	0	0
T86	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51964507	13349	0	0
T1	226213	66	0	0
T2	44169	7	0	0
T3	798644	0	0	0
T4	32003	3	0	0
T5	10302	4	0	0
T6	11781	0	0	0
T7	23304	0	0	0
T8	23371	0	0	0
T9	25820	3	0	0
T10	13570	0	0	0
T11	0	5	0	0
T13	0	8	0	0
T14	0	37	0	0
T15	0	90	0	0
T83	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51964507	1053	0	0
T2	44169	7	0	0
T3	798644	0	0	0
T4	32003	3	0	0
T5	10302	0	0	0
T6	11781	0	0	0
T7	23304	0	0	0
T8	23371	0	0	0
T9	25820	3	0	0
T10	13570	0	0	0
T13	0	8	0	0
T15	0	4	0	0
T18	23337	0	0	0
T26	0	12	0	0
T83	0	4	0	0
T84	0	4	0	0
T85	0	3	0	0
T86	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25983002	13375	0	0
T1	113102	66	0	0
T2	22084	10	0	0
T3	399346	0	0	0
T4	16002	3	0	0
T5	5150	4	0	0
T6	5890	0	0	0
T7	11660	0	0	0
T8	11684	0	0	0
T9	12910	4	0	0
T10	6785	0	0	0
T11	0	5	0	0
T13	0	11	0	0
T14	0	37	0	0
T15	0	91	0	0
T83	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25983002	1044	0	0
T2	22084	10	0	0
T3	399346	0	0	0
T4	16002	3	0	0
T5	5150	0	0	0
T6	5890	0	0	0
T7	11660	0	0	0
T8	11684	0	0	0
T9	12910	4	0	0
T10	6785	0	0	0
T13	0	11	0	0
T15	0	5	0	0
T18	11672	0	0	0
T26	0	11	0	0
T83	0	4	0	0
T84	0	5	0	0
T85	0	4	0	0
T86	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25983002	13375	0	0
T1	113102	66	0	0
T2	22084	10	0	0
T3	399346	0	0	0
T4	16002	3	0	0
T5	5150	4	0	0
T6	5890	0	0	0
T7	11660	0	0	0
T8	11684	0	0	0
T9	12910	4	0	0
T10	6785	0	0	0
T11	0	5	0	0
T13	0	11	0	0
T14	0	37	0	0
T15	0	91	0	0
T83	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25983002	1044	0	0
T2	22084	10	0	0
T3	399346	0	0	0
T4	16002	3	0	0
T5	5150	0	0	0
T6	5890	0	0	0
T7	11660	0	0	0
T8	11684	0	0	0
T9	12910	4	0	0
T10	6785	0	0	0
T13	0	11	0	0
T15	0	5	0	0
T18	11672	0	0	0
T26	0	11	0	0
T83	0	4	0	0
T84	0	5	0	0
T85	0	4	0	0
T86	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25982987	13462	0	0
T1	113099	66	0	0
T2	22084	11	0	0
T3	399345	0	0	0
T4	16002	5	0	0
T5	5152	4	0	0
T6	5890	0	0	0
T7	11657	0	0	0
T8	11682	0	0	0
T9	12909	4	0	0
T10	6785	0	0	0
T11	0	5	0	0
T13	0	10	0	0
T14	0	37	0	0
T15	0	91	0	0
T83	0	5	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25982987	1124	0	0
T2	22084	11	0	0
T3	399345	0	0	0
T4	16002	5	0	0
T5	5152	0	0	0
T6	5890	0	0	0
T7	11657	0	0	0
T8	11682	0	0	0
T9	12909	4	0	0
T10	6785	0	0	0
T13	0	10	0	0
T15	0	5	0	0
T18	11669	0	0	0
T26	0	12	0	0
T83	0	5	0	0
T84	0	6	0	0
T85	0	5	0	0
T87	0	10	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25982987	13462	0	0
T1	113099	66	0	0
T2	22084	11	0	0
T3	399345	0	0	0
T4	16002	5	0	0
T5	5152	4	0	0
T6	5890	0	0	0
T7	11657	0	0	0
T8	11682	0	0	0
T9	12909	4	0	0
T10	6785	0	0	0
T11	0	5	0	0
T13	0	10	0	0
T14	0	37	0	0
T15	0	91	0	0
T83	0	5	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25982987	1124	0	0
T2	22084	11	0	0
T3	399345	0	0	0
T4	16002	5	0	0
T5	5152	0	0	0
T6	5890	0	0	0
T7	11657	0	0	0
T8	11682	0	0	0
T9	12909	4	0	0
T10	6785	0	0	0
T13	0	10	0	0
T15	0	5	0	0
T18	11669	0	0	0
T26	0	12	0	0
T83	0	5	0	0
T84	0	6	0	0
T85	0	5	0	0
T87	0	10	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641819	22351	0	0
T1	7083	97	0	0
T2	1378	11	0	0
T3	25079	271	0	0
T4	998	7	0	0
T5	322	6	0	0
T6	368	2	0	0
T7	729	3	0	0
T8	732	3	0	0
T9	805	7	0	0
T10	423	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641819	1141	0	0
T2	1378	10	0	0
T3	25079	0	0	0
T4	998	6	0	0
T5	322	0	0	0
T6	368	0	0	0
T7	729	0	0	0
T8	732	0	0	0
T9	805	6	0	0
T10	423	0	0	0
T13	0	10	0	0
T15	0	3	0	0
T18	731	0	0	0
T26	0	12	0	0
T83	0	7	0	0
T84	0	8	0	0
T85	0	7	0	0
T87	0	11	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641819	22351	0	0
T1	7083	97	0	0
T2	1378	11	0	0
T3	25079	271	0	0
T4	998	7	0	0
T5	322	6	0	0
T6	368	2	0	0
T7	729	3	0	0
T8	732	3	0	0
T9	805	7	0	0
T10	423	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641819	1141	0	0
T2	1378	10	0	0
T3	25079	0	0	0
T4	998	6	0	0
T5	322	0	0	0
T6	368	0	0	0
T7	729	0	0	0
T8	732	0	0	0
T9	805	6	0	0
T10	423	0	0	0
T13	0	10	0	0
T15	0	3	0	0
T18	731	0	0	0
T26	0	12	0	0
T83	0	7	0	0
T84	0	8	0	0
T85	0	7	0	0
T87	0	11	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	14880	0	0
T1	56550	75	0	0
T2	11041	13	0	0
T3	199632	0	0	0
T4	8000	7	0	0
T5	2575	4	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	6	0	0
T10	3392	0	0	0
T11	0	5	0	0
T13	0	11	0	0
T14	0	40	0	0
T15	0	103	0	0
T83	0	7	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	1164	0	0
T2	11041	13	0	0
T3	199632	0	0	0
T4	8000	7	0	0
T5	2575	0	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	6	0	0
T10	3392	0	0	0
T13	0	11	0	0
T15	0	6	0	0
T18	5836	0	0	0
T26	0	9	0	0
T83	0	7	0	0
T84	0	9	0	0
T85	0	7	0	0
T87	0	12	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	14880	0	0
T1	56550	75	0	0
T2	11041	13	0	0
T3	199632	0	0	0
T4	8000	7	0	0
T5	2575	4	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	6	0	0
T10	3392	0	0	0
T11	0	5	0	0
T13	0	11	0	0
T14	0	40	0	0
T15	0	103	0	0
T83	0	7	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	1164	0	0
T2	11041	13	0	0
T3	199632	0	0	0
T4	8000	7	0	0
T5	2575	0	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	6	0	0
T10	3392	0	0	0
T13	0	11	0	0
T15	0	6	0	0
T18	5836	0	0	0
T26	0	9	0	0
T83	0	7	0	0
T84	0	9	0	0
T85	0	7	0	0
T87	0	12	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	14925	0	0
T1	56550	75	0	0
T2	11041	11	0	0
T3	199632	0	0	0
T4	8000	8	0	0
T5	2575	5	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	8	0	0
T10	3392	0	0	0
T11	0	5	0	0
T13	0	14	0	0
T14	0	40	0	0
T15	0	101	0	0
T83	0	7	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	1205	0	0
T2	11041	11	0	0
T3	199632	0	0	0
T4	8000	8	0	0
T5	2575	1	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	8	0	0
T10	3392	0	0	0
T13	0	14	0	0
T15	0	4	0	0
T18	5836	0	0	0
T26	0	9	0	0
T83	0	7	0	0
T84	0	11	0	0
T85	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	14925	0	0
T1	56550	75	0	0
T2	11041	11	0	0
T3	199632	0	0	0
T4	8000	8	0	0
T5	2575	5	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	8	0	0
T10	3392	0	0	0
T11	0	5	0	0
T13	0	14	0	0
T14	0	40	0	0
T15	0	101	0	0
T83	0	7	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	1205	0	0
T2	11041	11	0	0
T3	199632	0	0	0
T4	8000	8	0	0
T5	2575	1	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	8	0	0
T10	3392	0	0	0
T13	0	14	0	0
T15	0	4	0	0
T18	5836	0	0	0
T26	0	9	0	0
T83	0	7	0	0
T84	0	11	0	0
T85	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	15013	0	0
T1	56550	75	0	0
T2	11041	13	0	0
T3	199632	0	0	0
T4	8000	7	0	0
T5	2575	5	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	9	0	0
T10	3392	0	0	0
T11	0	5	0	0
T13	0	13	0	0
T14	0	40	0	0
T15	0	102	0	0
T83	0	9	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	1294	0	0
T2	11041	13	0	0
T3	199632	0	0	0
T4	8000	7	0	0
T5	2575	1	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	9	0	0
T10	3392	0	0	0
T13	0	13	0	0
T15	0	5	0	0
T18	5836	0	0	0
T26	0	13	0	0
T83	0	9	0	0
T84	0	12	0	0
T85	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	15013	0	0
T1	56550	75	0	0
T2	11041	13	0	0
T3	199632	0	0	0
T4	8000	7	0	0
T5	2575	5	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	9	0	0
T10	3392	0	0	0
T11	0	5	0	0
T13	0	13	0	0
T14	0	40	0	0
T15	0	102	0	0
T83	0	9	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12991121	1294	0	0
T2	11041	13	0	0
T3	199632	0	0	0
T4	8000	7	0	0
T5	2575	1	0	0
T6	2944	0	0	0
T7	5823	0	0	0
T8	5839	0	0	0
T9	6454	9	0	0
T10	3392	0	0	0
T13	0	13	0	0
T15	0	5	0	0
T18	5836	0	0	0
T26	0	13	0	0
T83	0	9	0	0
T84	0	12	0	0
T85	0	10	0	0