Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12223349	8466	0	0
alert_regwen_rd_A	12223349	3343	0	0
cpu_regwen_rd_A	12223349	3577	0	0
sw_rst_ctrl_n_0_rd_A	12223349	8588	0	0
sw_rst_ctrl_n_1_rd_A	12223349	8820	0	0
sw_rst_ctrl_n_2_rd_A	12223349	8577	0	0
sw_rst_ctrl_n_3_rd_A	12223349	8369	0	0
sw_rst_ctrl_n_4_rd_A	12223349	8510	0	0
sw_rst_ctrl_n_5_rd_A	12223349	8464	0	0
sw_rst_ctrl_n_6_rd_A	12223349	8745	0	0
sw_rst_ctrl_n_7_rd_A	12223349	8734	0	0
sw_rst_regwen_0_rd_A	12223349	4013	0	0
sw_rst_regwen_1_rd_A	12223349	4086	0	0
sw_rst_regwen_2_rd_A	12223349	4119	0	0
sw_rst_regwen_3_rd_A	12223349	4327	0	0
sw_rst_regwen_4_rd_A	12223349	4207	0	0
sw_rst_regwen_5_rd_A	12223349	4191	0	0
sw_rst_regwen_6_rd_A	12223349	4022	0	0
sw_rst_regwen_7_rd_A	12223349	4322	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	8466	0	0
T64	4208	15	0	0
T66	3081	8	0	0
T68	4825	18	0	0
T69	2571	5	0	0
T70	14044	749	0	0
T71	5236	180	0	0
T72	3074	121	0	0
T73	4999	213	0	0
T91	2079	3	0	0
T92	4001	346	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	3343	0	0
T14	39866	71	0	0
T15	89067	0	0	0
T16	4328	0	0	0
T17	33062	24	0	0
T26	276240	240	0	0
T27	3529	0	0	0
T29	5099	0	0	0
T56	1995	0	0	0
T83	9871	0	0	0
T84	7303	0	0	0
T93	0	135	0	0
T97	0	70	0	0
T98	0	55	0	0
T99	0	65	0	0
T121	0	41	0	0
T122	0	37	0	0
T123	0	29	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	3577	0	0
T14	39866	63	0	0
T15	89067	0	0	0
T16	4328	0	0	0
T17	33062	15	0	0
T26	276240	247	0	0
T27	3529	0	0	0
T29	5099	0	0	0
T56	1995	0	0	0
T83	9871	0	0	0
T84	7303	0	0	0
T93	0	185	0	0
T97	0	78	0	0
T98	0	39	0	0
T99	0	55	0	0
T121	0	65	0	0
T122	0	59	0	0
T123	0	33	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	8588	0	0
T2	10975	117	0	0
T3	194151	0	0	0
T4	7981	82	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	59	0	0
T16	0	44	0	0
T17	0	23	0	0
T18	5289	0	0	0
T26	0	286	0	0
T83	0	134	0	0
T85	0	111	0	0
T87	0	183	0	0
T124	0	151	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	8820	0	0
T2	10975	128	0	0
T3	194151	0	0	0
T4	7981	111	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	80	0	0
T16	0	60	0	0
T17	0	36	0	0
T18	5289	0	0	0
T26	0	398	0	0
T83	0	132	0	0
T85	0	117	0	0
T87	0	198	0	0
T124	0	94	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	8577	0	0
T2	10975	154	0	0
T3	194151	0	0	0
T4	7981	94	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	62	0	0
T16	0	56	0	0
T17	0	27	0	0
T18	5289	0	0	0
T26	0	323	0	0
T83	0	132	0	0
T85	0	152	0	0
T87	0	224	0	0
T124	0	120	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	8369	0	0
T2	10975	127	0	0
T3	194151	0	0	0
T4	7981	70	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	48	0	0
T16	0	47	0	0
T17	0	29	0	0
T18	5289	0	0	0
T26	0	317	0	0
T83	0	135	0	0
T85	0	91	0	0
T87	0	167	0	0
T124	0	117	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	8510	0	0
T2	10975	104	0	0
T3	194151	0	0	0
T4	7981	97	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	46	0	0
T16	0	34	0	0
T17	0	18	0	0
T18	5289	0	0	0
T26	0	364	0	0
T83	0	122	0	0
T85	0	129	0	0
T87	0	208	0	0
T124	0	121	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	8464	0	0
T2	10975	149	0	0
T3	194151	0	0	0
T4	7981	60	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	59	0	0
T16	0	36	0	0
T17	0	29	0	0
T18	5289	0	0	0
T26	0	372	0	0
T83	0	122	0	0
T85	0	141	0	0
T87	0	180	0	0
T124	0	103	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	8745	0	0
T2	10975	133	0	0
T3	194151	0	0	0
T4	7981	82	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	78	0	0
T16	0	63	0	0
T17	0	22	0	0
T18	5289	0	0	0
T26	0	390	0	0
T83	0	167	0	0
T85	0	159	0	0
T87	0	237	0	0
T124	0	126	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	8734	0	0
T2	10975	116	0	0
T3	194151	0	0	0
T4	7981	57	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	63	0	0
T16	0	60	0	0
T17	0	31	0	0
T18	5289	0	0	0
T26	0	356	0	0
T83	0	155	0	0
T85	0	142	0	0
T87	0	197	0	0
T124	0	109	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	4013	0	0
T2	10975	21	0	0
T3	194151	0	0	0
T4	7981	17	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	50	0	0
T17	0	21	0	0
T18	5289	0	0	0
T26	0	295	0	0
T83	0	39	0	0
T85	0	37	0	0
T87	0	22	0	0
T93	0	149	0	0
T124	0	23	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	4086	0	0
T2	10975	23	0	0
T3	194151	0	0	0
T4	7981	18	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	64	0	0
T17	0	21	0	0
T18	5289	0	0	0
T26	0	236	0	0
T83	0	34	0	0
T85	0	20	0	0
T87	0	35	0	0
T93	0	171	0	0
T124	0	39	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	4119	0	0
T2	10975	18	0	0
T3	194151	0	0	0
T4	7981	23	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	60	0	0
T17	0	23	0	0
T18	5289	0	0	0
T26	0	244	0	0
T83	0	33	0	0
T85	0	27	0	0
T87	0	36	0	0
T93	0	179	0	0
T124	0	28	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	4327	0	0
T2	10975	13	0	0
T3	194151	0	0	0
T4	7981	28	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	52	0	0
T17	0	24	0	0
T18	5289	0	0	0
T26	0	235	0	0
T83	0	30	0	0
T85	0	28	0	0
T87	0	36	0	0
T93	0	188	0	0
T124	0	36	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	4207	0	0
T2	10975	13	0	0
T3	194151	0	0	0
T4	7981	12	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	49	0	0
T17	0	26	0	0
T18	5289	0	0	0
T26	0	248	0	0
T83	0	34	0	0
T85	0	54	0	0
T87	0	31	0	0
T93	0	143	0	0
T124	0	46	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	4191	0	0
T2	10975	22	0	0
T3	194151	0	0	0
T4	7981	14	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	69	0	0
T17	0	15	0	0
T18	5289	0	0	0
T26	0	249	0	0
T83	0	30	0	0
T85	0	56	0	0
T87	0	27	0	0
T93	0	168	0	0
T124	0	29	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	4022	0	0
T2	10975	26	0	0
T3	194151	0	0	0
T4	7981	27	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	83	0	0
T17	0	20	0	0
T18	5289	0	0	0
T26	0	231	0	0
T83	0	32	0	0
T85	0	24	0	0
T87	0	40	0	0
T93	0	131	0	0
T124	0	31	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12223349	4322	0	0
T2	10975	3	0	0
T3	194151	0	0	0
T4	7981	9	0	0
T5	2476	0	0	0
T6	2782	0	0	0
T7	5090	0	0	0
T8	5488	0	0	0
T9	6364	0	0	0
T10	3349	0	0	0
T14	0	37	0	0
T17	0	42	0	0
T18	5289	0	0	0
T26	0	265	0	0
T83	0	33	0	0
T85	0	13	0	0
T87	0	48	0	0
T93	0	151	0	0
T124	0	30	0	0