Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	571220	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

345796

1

T1

1145

T2

265

T3

1132

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	487104	1			T1	1786		T2	379		T3	1597
values[0x0]	214836	1			T1	659		T2	171		T3	701
values[0x1]	215076	1			T1	676		T2	162		T3	747

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	479327	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

437689

1

T1

1450

T2

326

T3

1422

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3438	1			T1	9		T2	2		T4	1
valid_sources[0x01]	3245	1			T1	13		T2	2		T4	3
valid_sources[0x02]	2864	1			T1	10		T2	1		T4	3
valid_sources[0x03]	2946	1			T1	15		T2	5		T4	2
valid_sources[0x04]	3092	1			T1	10		T2	4		T4	1
valid_sources[0x05]	3316	1			T1	11		T2	1		T10	4
valid_sources[0x06]	3604	1			T1	9		T2	3		T10	4
valid_sources[0x07]	3272	1			T1	15		T2	5		T4	1
valid_sources[0x08]	2908	1			T1	21		T2	6		T4	2
valid_sources[0x09]	4178	1			T1	9		T2	1		T6	1
valid_sources[0x0a]	3730	1			T1	9		T2	5		T4	1
valid_sources[0x0b]	3687	1			T1	15		T4	1		T6	3
valid_sources[0x0c]	2793	1			T1	15		T2	1		T4	1
valid_sources[0x0d]	2800	1			T1	12		T2	1		T4	1
valid_sources[0x0e]	3458	1			T1	9		T2	4		T7	3
valid_sources[0x0f]	3428	1			T1	13		T2	1		T4	2
valid_sources[0x10]	2814	1			T1	7		T2	5		T4	1
valid_sources[0x11]	4268	1			T1	14		T2	4		T4	1
valid_sources[0x12]	3231	1			T1	13		T2	2		T4	1
valid_sources[0x13]	3135	1			T1	11		T2	3		T4	2
valid_sources[0x14]	2789	1			T1	13		T2	2		T6	2
valid_sources[0x15]	3548	1			T1	14		T7	1		T10	4
valid_sources[0x16]	4043	1			T1	19		T2	2		T4	1
valid_sources[0x17]	3179	1			T1	14		T4	3		T6	1
valid_sources[0x18]	3103	1			T1	8		T2	4		T10	5
valid_sources[0x19]	2874	1			T1	13		T2	2		T4	1
valid_sources[0x1a]	3033	1			T1	10		T2	1		T4	1
valid_sources[0x1b]	3290	1			T1	14		T2	6		T10	2
valid_sources[0x1c]	3736	1			T1	19		T2	3		T4	1
valid_sources[0x1d]	3709	1			T1	19		T4	1		T6	6
valid_sources[0x1e]	2985	1			T1	16		T2	4		T4	1
valid_sources[0x1f]	3994	1			T1	10		T2	7		T4	1
valid_sources[0x20]	3641	1			T1	13		T2	4		T6	1
valid_sources[0x21]	3078	1			T1	14		T2	2		T7	2
valid_sources[0x22]	3844	1			T1	18		T2	3		T6	1
valid_sources[0x23]	4380	1			T1	6		T7	2		T10	2
valid_sources[0x24]	3487	1			T1	8		T3	70		T6	1
valid_sources[0x25]	3194	1			T1	10		T6	1		T7	5
valid_sources[0x26]	3499	1			T1	9		T7	1		T9	2
valid_sources[0x27]	3199	1			T1	10		T2	1		T6	4
valid_sources[0x28]	3243	1			T1	22		T2	1		T6	5
valid_sources[0x29]	3479	1			T1	11		T2	5		T4	1
valid_sources[0x2a]	2641	1			T1	14		T2	9		T4	1
valid_sources[0x2b]	3730	1			T1	17		T2	2		T4	1
valid_sources[0x2c]	2916	1			T1	7		T2	2		T4	3
valid_sources[0x2d]	4236	1			T1	10		T2	5		T4	2
valid_sources[0x2e]	3767	1			T1	7		T2	2		T3	197
valid_sources[0x2f]	3957	1			T1	8		T2	3		T4	1
valid_sources[0x30]	2834	1			T1	12		T2	2		T7	2
valid_sources[0x31]	2946	1			T1	9		T2	3		T4	1
valid_sources[0x32]	2817	1			T1	12		T2	1		T6	3
valid_sources[0x33]	3055	1			T1	13		T2	1		T4	1
valid_sources[0x34]	3314	1			T1	11		T2	4		T4	3
valid_sources[0x35]	3117	1			T1	5		T2	1		T7	5
valid_sources[0x36]	3331	1			T1	11		T2	5		T6	3
valid_sources[0x37]	3252	1			T1	15		T2	1		T4	1
valid_sources[0x38]	3708	1			T1	10		T2	6		T9	9
valid_sources[0x39]	3245	1			T1	5		T2	4		T6	1
valid_sources[0x3a]	3039	1			T1	13		T2	4		T4	1
valid_sources[0x3b]	3488	1			T1	10		T2	5		T4	2
valid_sources[0x3c]	3600	1			T1	16		T7	4		T10	5
valid_sources[0x3d]	3815	1			T1	12		T2	5		T7	2
valid_sources[0x3e]	2906	1			T1	10		T2	1		T4	2
valid_sources[0x3f]	2674	1			T1	8		T2	6		T6	4
valid_sources[0x40]	2921	1			T1	16		T2	3		T4	1
valid_sources[0x41]	3765	1			T1	11		T4	1		T9	1
valid_sources[0x42]	3439	1			T1	10		T2	1		T7	8
valid_sources[0x43]	3112	1			T1	11		T2	2		T6	1
valid_sources[0x44]	3369	1			T1	6		T2	2		T7	6
valid_sources[0x45]	4853	1			T1	19		T2	7		T7	2
valid_sources[0x46]	3079	1			T1	6		T2	2		T4	3
valid_sources[0x47]	2733	1			T1	20		T2	4		T4	1
valid_sources[0x48]	3487	1			T1	15		T2	2		T7	1
valid_sources[0x49]	3730	1			T1	6		T2	4		T6	1
valid_sources[0x4a]	4415	1			T1	25		T2	4		T4	1
valid_sources[0x4b]	3866	1			T1	10		T2	2		T4	2
valid_sources[0x4c]	3553	1			T1	5		T2	6		T4	1
valid_sources[0x4d]	4048	1			T1	17		T2	1		T9	1
valid_sources[0x4e]	3229	1			T1	8		T2	2		T4	7
valid_sources[0x4f]	3291	1			T1	15		T10	2		T12	20
valid_sources[0x50]	4714	1			T1	11		T2	2		T3	154
valid_sources[0x51]	5484	1			T1	16		T2	4		T4	2
valid_sources[0x52]	3327	1			T1	9		T2	1		T4	1
valid_sources[0x53]	3253	1			T1	16		T2	2		T10	2
valid_sources[0x54]	3206	1			T1	6		T2	1		T4	1
valid_sources[0x55]	5477	1			T1	14		T2	3		T7	7
valid_sources[0x56]	2893	1			T1	10		T2	4		T7	1
valid_sources[0x57]	3492	1			T1	14		T2	2		T6	2
valid_sources[0x58]	3723	1			T1	17		T2	5		T4	1
valid_sources[0x59]	3657	1			T1	15		T2	3		T10	3
valid_sources[0x5a]	4164	1			T1	17		T2	1		T10	4
valid_sources[0x5b]	2969	1			T1	9		T6	7		T7	9
valid_sources[0x5c]	4008	1			T1	13		T3	960		T4	1
valid_sources[0x5d]	3006	1			T1	10		T2	5		T4	1
valid_sources[0x5e]	3915	1			T1	7		T2	4		T6	1
valid_sources[0x5f]	3442	1			T1	12		T2	3		T6	3
valid_sources[0x60]	3464	1			T1	13		T2	2		T3	467
valid_sources[0x61]	3018	1			T1	12		T2	3		T9	1
valid_sources[0x62]	3076	1			T1	12		T2	2		T10	2
valid_sources[0x63]	3235	1			T1	23		T2	9		T6	2
valid_sources[0x64]	3062	1			T1	16		T10	5		T12	8
valid_sources[0x65]	3366	1			T1	14		T2	5		T9	1
valid_sources[0x66]	3480	1			T1	11		T2	2		T4	1
valid_sources[0x67]	3352	1			T1	20		T2	3		T3	2
valid_sources[0x68]	3178	1			T1	13		T2	2		T6	2
valid_sources[0x69]	3448	1			T1	10		T4	1		T10	1
valid_sources[0x6a]	3992	1			T1	13		T2	2		T4	1
valid_sources[0x6b]	3611	1			T1	8		T2	1		T6	1
valid_sources[0x6c]	3570	1			T1	12		T4	1		T6	5
valid_sources[0x6d]	3214	1			T1	12		T2	3		T7	6
valid_sources[0x6e]	4526	1			T1	12		T2	4		T4	1
valid_sources[0x6f]	6705	1			T1	13		T2	3		T10	7
valid_sources[0x70]	5300	1			T1	9		T2	5		T4	2
valid_sources[0x71]	3514	1			T1	20		T2	3		T4	1
valid_sources[0x72]	5610	1			T1	15		T2	2		T6	1
valid_sources[0x73]	4063	1			T1	11		T2	6		T9	4
valid_sources[0x74]	3690	1			T1	14		T2	3		T4	2
valid_sources[0x75]	6157	1			T1	9		T2	1		T4	1
valid_sources[0x76]	2807	1			T1	10		T4	1		T10	6
valid_sources[0x77]	4256	1			T1	19		T2	2		T7	2
valid_sources[0x78]	3404	1			T1	6		T2	4		T4	2
valid_sources[0x79]	5109	1			T1	10		T2	1		T10	5
valid_sources[0x7a]	2925	1			T1	16		T2	4		T4	1
valid_sources[0x7b]	4166	1			T1	12		T2	7		T4	2
valid_sources[0x7c]	3327	1			T1	6		T4	1		T6	3
valid_sources[0x7d]	3642	1			T1	7		T2	3		T10	6
valid_sources[0x7e]	3750	1			T1	15		T2	5		T9	4
valid_sources[0x7f]	3754	1			T1	14		T2	3		T10	3
valid_sources[0x80]	6504	1			T1	14		T2	5		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

228421

1

T1

815

T2

186

T3

751

values[0x0]

all_enables

biggest_size

76068

1

T1

228

T2

55

T3

244

values[0x1]

all_enables

biggest_size

41307

1

T1

102

T2

24

T3

137