Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	10920397	12347	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	10920397	113837	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	10920397	6115259	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	10920397	182191	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	10920397	12347	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	10920397	113837	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	10920397	6115259	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	10920397	182191	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	12347	0	0
T1	33960	37	0	0
T2	6372	0	0	0
T3	34012	38	0	0
T4	3299	4	0	0
T5	5669	0	0	0
T6	3498	14	0	0
T7	2434	4	0	0
T8	1699	0	0	0
T9	2239	4	0	0
T10	8451	0	0	0
T12	0	37	0	0
T13	0	75	0	0
T14	0	4	0	0
T15	0	75	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	113837	0	0
T1	33960	341	0	0
T2	6372	0	0	0
T3	34012	349	0	0
T4	3299	38	0	0
T5	5669	0	0	0
T6	3498	126	0	0
T7	2434	37	0	0
T8	1699	0	0	0
T9	2239	37	0	0
T10	8451	0	0	0
T12	0	338	0	0
T13	0	717	0	0
T14	0	37	0	0
T15	0	710	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	6115259	0	0
T1	33960	23390	0	0
T2	6372	5780	0	0
T3	34012	26878	0	0
T4	3299	2351	0	0
T5	5669	578	0	0
T6	3498	2643	0	0
T7	2434	1449	0	0
T8	1699	1102	0	0
T9	2239	1225	0	0
T10	8451	7850	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	182191	0	0
T1	33960	522	0	0
T2	6372	0	0	0
T3	34012	575	0	0
T4	3299	70	0	0
T5	5669	0	0	0
T6	3498	203	0	0
T7	2434	55	0	0
T8	1699	0	0	0
T9	2239	61	0	0
T10	8451	0	0	0
T12	0	531	0	0
T13	0	1143	0	0
T14	0	74	0	0
T15	0	1136	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	12347	0	0
T1	33960	37	0	0
T2	6372	0	0	0
T3	34012	38	0	0
T4	3299	4	0	0
T5	5669	0	0	0
T6	3498	14	0	0
T7	2434	4	0	0
T8	1699	0	0	0
T9	2239	4	0	0
T10	8451	0	0	0
T12	0	37	0	0
T13	0	75	0	0
T14	0	4	0	0
T15	0	75	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	113837	0	0
T1	33960	341	0	0
T2	6372	0	0	0
T3	34012	349	0	0
T4	3299	38	0	0
T5	5669	0	0	0
T6	3498	126	0	0
T7	2434	37	0	0
T8	1699	0	0	0
T9	2239	37	0	0
T10	8451	0	0	0
T12	0	338	0	0
T13	0	717	0	0
T14	0	37	0	0
T15	0	710	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	6115259	0	0
T1	33960	23390	0	0
T2	6372	5780	0	0
T3	34012	26878	0	0
T4	3299	2351	0	0
T5	5669	578	0	0
T6	3498	2643	0	0
T7	2434	1449	0	0
T8	1699	1102	0	0
T9	2239	1225	0	0
T10	8451	7850	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	182191	0	0
T1	33960	522	0	0
T2	6372	0	0	0
T3	34012	575	0	0
T4	3299	70	0	0
T5	5669	0	0	0
T6	3498	203	0	0
T7	2434	55	0	0
T8	1699	0	0	0
T9	2239	61	0	0
T10	8451	0	0	0
T12	0	531	0	0
T13	0	1143	0	0
T14	0	74	0	0
T15	0	1136	0	0