Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T3,T7

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	51173999	8675	0	0
CascadeEffAonToRstPorAboveRise_A	51173999	8675	0	0
CascadeEffAonToRstPorIoAboveFall_A	49125464	8675	0	0
CascadeEffAonToRstPorIoAboveRise_A	49125464	8675	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24563269	8675	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24563269	8675	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12281212	8675	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12281212	8675	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24563339	8675	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24563339	8675	0	0
CascadeLcToLcAboveFall_A	51173999	21022	0	0
CascadeLcToLcAboveRise_A	51173999	21022	0	0
CascadeLcToLcAonAboveFall_A	1550633	21022	0	0
CascadeLcToLcAonAboveRise_A	1550633	21022	0	0
CascadeLcToLcShadowedAboveFall_A	51173999	21022	0	0
CascadeLcToLcShadowedAboveRise_A	51173999	21022	0	0
CascadePorToAonAboveFall_A	1550633	7129	0	0
CascadeSysToSysAboveFall_A	51173999	21022	0	0
CascadeSysToSysAboveRise_A	51173999	21022	0	0
ScanRstToAonRise_A	1550633	212	0	0
StablePorToAonRise_A	1550633	8675	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10920397	21022	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10920397	21022	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10920397	21022	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10920397	21022	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12281212	21022	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12281212	21022	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10920397	21022	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10920397	21022	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10920397	21022	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10920397	21022	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51173999	8675	0	0
T1	166032	23	0	0
T2	26835	1	0	0
T3	160963	15	0	0
T4	14943	2	0	0
T5	24307	8	0	0
T6	18864	1	0	0
T7	10931	2	0	0
T8	7360	1	0	0
T9	10143	2	0	0
T10	35494	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51173999	8675	0	0
T1	166032	23	0	0
T2	26835	1	0	0
T3	160963	15	0	0
T4	14943	2	0	0
T5	24307	8	0	0
T6	18864	1	0	0
T7	10931	2	0	0
T8	7360	1	0	0
T9	10143	2	0	0
T10	35494	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49125464	8675	0	0
T1	159381	23	0	0
T2	25760	1	0	0
T3	154524	15	0	0
T4	14346	2	0	0
T5	23328	8	0	0
T6	18109	1	0	0
T7	10494	2	0	0
T8	7065	1	0	0
T9	9741	2	0	0
T10	34073	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49125464	8675	0	0
T1	159381	23	0	0
T2	25760	1	0	0
T3	154524	15	0	0
T4	14346	2	0	0
T5	23328	8	0	0
T6	18109	1	0	0
T7	10494	2	0	0
T8	7065	1	0	0
T9	9741	2	0	0
T10	34073	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563269	8675	0	0
T1	79688	23	0	0
T2	12880	1	0	0
T3	77265	15	0	0
T4	7173	2	0	0
T5	11657	8	0	0
T6	9054	1	0	0
T7	5245	2	0	0
T8	3532	1	0	0
T9	4868	2	0	0
T10	17038	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563269	8675	0	0
T1	79688	23	0	0
T2	12880	1	0	0
T3	77265	15	0	0
T4	7173	2	0	0
T5	11657	8	0	0
T6	9054	1	0	0
T7	5245	2	0	0
T8	3532	1	0	0
T9	4868	2	0	0
T10	17038	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	8675	0	0
T1	39843	23	0	0
T2	6440	1	0	0
T3	38627	15	0	0
T4	3586	2	0	0
T5	5830	8	0	0
T6	4526	1	0	0
T7	2623	2	0	0
T8	1765	1	0	0
T9	2433	2	0	0
T10	8517	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	8675	0	0
T1	39843	23	0	0
T2	6440	1	0	0
T3	38627	15	0	0
T4	3586	2	0	0
T5	5830	8	0	0
T6	4526	1	0	0
T7	2623	2	0	0
T8	1765	1	0	0
T9	2433	2	0	0
T10	8517	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563339	8675	0	0
T1	79683	23	0	0
T2	12881	1	0	0
T3	77262	15	0	0
T4	7170	2	0	0
T5	11668	8	0	0
T6	9054	1	0	0
T7	5245	2	0	0
T8	3532	1	0	0
T9	4866	2	0	0
T10	17037	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563339	8675	0	0
T1	79683	23	0	0
T2	12881	1	0	0
T3	77262	15	0	0
T4	7170	2	0	0
T5	11668	8	0	0
T6	9054	1	0	0
T7	5245	2	0	0
T8	3532	1	0	0
T9	4866	2	0	0
T10	17037	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51173999	21022	0	0
T1	166032	60	0	0
T2	26835	1	0	0
T3	160963	53	0	0
T4	14943	6	0	0
T5	24307	8	0	0
T6	18864	15	0	0
T7	10931	6	0	0
T8	7360	1	0	0
T9	10143	6	0	0
T10	35494	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51173999	21022	0	0
T1	166032	60	0	0
T2	26835	1	0	0
T3	160963	53	0	0
T4	14943	6	0	0
T5	24307	8	0	0
T6	18864	15	0	0
T7	10931	6	0	0
T8	7360	1	0	0
T9	10143	6	0	0
T10	35494	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550633	21022	0	0
T1	5040	60	0	0
T2	804	1	0	0
T3	4889	53	0	0
T4	446	6	0	0
T5	731	8	0	0
T6	564	15	0	0
T7	326	6	0	0
T8	219	1	0	0
T9	303	6	0	0
T10	1063	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550633	21022	0	0
T1	5040	60	0	0
T2	804	1	0	0
T3	4889	53	0	0
T4	446	6	0	0
T5	731	8	0	0
T6	564	15	0	0
T7	326	6	0	0
T8	219	1	0	0
T9	303	6	0	0
T10	1063	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51173999	21022	0	0
T1	166032	60	0	0
T2	26835	1	0	0
T3	160963	53	0	0
T4	14943	6	0	0
T5	24307	8	0	0
T6	18864	15	0	0
T7	10931	6	0	0
T8	7360	1	0	0
T9	10143	6	0	0
T10	35494	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51173999	21022	0	0
T1	166032	60	0	0
T2	26835	1	0	0
T3	160963	53	0	0
T4	14943	6	0	0
T5	24307	8	0	0
T6	18864	15	0	0
T7	10931	6	0	0
T8	7360	1	0	0
T9	10143	6	0	0
T10	35494	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550633	7129	0	0
T1	5040	12	0	0
T2	804	1	0	0
T3	4889	8	0	0
T4	446	1	0	0
T5	731	8	0	0
T6	564	1	0	0
T7	326	1	0	0
T8	219	1	0	0
T9	303	1	0	0
T10	1063	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51173999	21022	0	0
T1	166032	60	0	0
T2	26835	1	0	0
T3	160963	53	0	0
T4	14943	6	0	0
T5	24307	8	0	0
T6	18864	15	0	0
T7	10931	6	0	0
T8	7360	1	0	0
T9	10143	6	0	0
T10	35494	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51173999	21022	0	0
T1	166032	60	0	0
T2	26835	1	0	0
T3	160963	53	0	0
T4	14943	6	0	0
T5	24307	8	0	0
T6	18864	15	0	0
T7	10931	6	0	0
T8	7360	1	0	0
T9	10143	6	0	0
T10	35494	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550633	212	0	0
T12	2737	2	0	0
T13	6472	0	0	0
T14	767	1	0	0
T15	3682	0	0	0
T16	728	0	0	0
T17	731	0	0	0
T45	201	0	0	0
T46	838	0	0	0
T47	2637	0	0	0
T48	251	0	0	0
T59	0	2	0	0
T66	0	1	0	0
T68	0	2	0	0
T89	0	2	0	0
T91	0	1	0	0
T92	0	4	0	0
T101	0	3	0	0
T145	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550633	8675	0	0
T1	5040	23	0	0
T2	804	1	0	0
T3	4889	15	0	0
T4	446	2	0	0
T5	731	8	0	0
T6	564	1	0	0
T7	326	2	0	0
T8	219	1	0	0
T9	303	2	0	0
T10	1063	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	21022	0	0
T1	33960	60	0	0
T2	6372	1	0	0
T3	34012	53	0	0
T4	3299	6	0	0
T5	5669	8	0	0
T6	3498	15	0	0
T7	2434	6	0	0
T8	1699	1	0	0
T9	2239	6	0	0
T10	8451	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	21022	0	0
T1	33960	60	0	0
T2	6372	1	0	0
T3	34012	53	0	0
T4	3299	6	0	0
T5	5669	8	0	0
T6	3498	15	0	0
T7	2434	6	0	0
T8	1699	1	0	0
T9	2239	6	0	0
T10	8451	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	21022	0	0
T1	33960	60	0	0
T2	6372	1	0	0
T3	34012	53	0	0
T4	3299	6	0	0
T5	5669	8	0	0
T6	3498	15	0	0
T7	2434	6	0	0
T8	1699	1	0	0
T9	2239	6	0	0
T10	8451	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	21022	0	0
T1	33960	60	0	0
T2	6372	1	0	0
T3	34012	53	0	0
T4	3299	6	0	0
T5	5669	8	0	0
T6	3498	15	0	0
T7	2434	6	0	0
T8	1699	1	0	0
T9	2239	6	0	0
T10	8451	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	21022	0	0
T1	39843	60	0	0
T2	6440	1	0	0
T3	38627	53	0	0
T4	3586	6	0	0
T5	5830	8	0	0
T6	4526	15	0	0
T7	2623	6	0	0
T8	1765	1	0	0
T9	2433	6	0	0
T10	8517	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	21022	0	0
T1	39843	60	0	0
T2	6440	1	0	0
T3	38627	53	0	0
T4	3586	6	0	0
T5	5830	8	0	0
T6	4526	15	0	0
T7	2623	6	0	0
T8	1765	1	0	0
T9	2433	6	0	0
T10	8517	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	21022	0	0
T1	33960	60	0	0
T2	6372	1	0	0
T3	34012	53	0	0
T4	3299	6	0	0
T5	5669	8	0	0
T6	3498	15	0	0
T7	2434	6	0	0
T8	1699	1	0	0
T9	2239	6	0	0
T10	8451	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	21022	0	0
T1	33960	60	0	0
T2	6372	1	0	0
T3	34012	53	0	0
T4	3299	6	0	0
T5	5669	8	0	0
T6	3498	15	0	0
T7	2434	6	0	0
T8	1699	1	0	0
T9	2239	6	0	0
T10	8451	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	21022	0	0
T1	33960	60	0	0
T2	6372	1	0	0
T3	34012	53	0	0
T4	3299	6	0	0
T5	5669	8	0	0
T6	3498	15	0	0
T7	2434	6	0	0
T8	1699	1	0	0
T9	2239	6	0	0
T10	8451	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10920397	21022	0	0
T1	33960	60	0	0
T2	6372	1	0	0
T3	34012	53	0	0
T4	3299	6	0	0
T5	5669	8	0	0
T6	3498	15	0	0
T7	2434	6	0	0
T8	1699	1	0	0
T9	2239	6	0	0
T10	8451	1	0	0