Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12281212	13159	0	0
gen_assertions[0].RstEnOn_A	12281212	1032	0	0
gen_assertions[0].RstNOff_A	12281212	13159	0	0
gen_assertions[0].RstNOn_A	12281212	1032	0	0
gen_assertions[1].RstEnOff_A	49125464	11966	0	0
gen_assertions[1].RstEnOn_A	49125464	948	0	0
gen_assertions[1].RstNOff_A	49125464	11966	0	0
gen_assertions[1].RstNOn_A	49125464	948	0	0
gen_assertions[2].RstEnOff_A	24563269	12019	0	0
gen_assertions[2].RstEnOn_A	24563269	942	0	0
gen_assertions[2].RstNOff_A	24563269	12019	0	0
gen_assertions[2].RstNOn_A	24563269	942	0	0
gen_assertions[3].RstEnOff_A	24563339	12061	0	0
gen_assertions[3].RstEnOn_A	24563339	959	0	0
gen_assertions[3].RstNOff_A	24563339	12061	0	0
gen_assertions[3].RstNOn_A	24563339	959	0	0
gen_assertions[4].RstEnOff_A	1550633	20713	0	0
gen_assertions[4].RstEnOn_A	1550633	978	0	0
gen_assertions[4].RstNOff_A	1550633	20713	0	0
gen_assertions[4].RstNOn_A	1550633	978	0	0
gen_assertions[5].RstEnOff_A	12281212	13383	0	0
gen_assertions[5].RstEnOn_A	12281212	1075	0	0
gen_assertions[5].RstNOff_A	12281212	13383	0	0
gen_assertions[5].RstNOn_A	12281212	1075	0	0
gen_assertions[6].RstEnOff_A	12281212	13427	0	0
gen_assertions[6].RstEnOn_A	12281212	1124	0	0
gen_assertions[6].RstNOff_A	12281212	13427	0	0
gen_assertions[6].RstNOn_A	12281212	1124	0	0
gen_assertions[7].RstEnOff_A	12281212	13480	0	0
gen_assertions[7].RstEnOn_A	12281212	1170	0	0
gen_assertions[7].RstNOff_A	12281212	13480	0	0
gen_assertions[7].RstNOn_A	12281212	1170	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	13159	0	0
T1	39843	37	0	0
T2	6440	2	0	0
T3	38627	48	0	0
T4	3586	4	0	0
T5	5830	0	0	0
T6	4526	14	0	0
T7	2623	5	0	0
T8	1765	0	0	0
T9	2433	4	0	0
T10	8517	6	0	0
T11	0	1	0	0
T12	0	37	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	1032	0	0
T2	6440	2	0	0
T3	38627	11	0	0
T4	3586	0	0	0
T5	5830	0	0	0
T6	4526	2	0	0
T7	2623	1	0	0
T8	1765	0	0	0
T9	2433	0	0	0
T10	8517	6	0	0
T11	3509	1	0	0
T14	0	1	0	0
T46	0	2	0	0
T50	0	1	0	0
T61	0	13	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	13159	0	0
T1	39843	37	0	0
T2	6440	2	0	0
T3	38627	48	0	0
T4	3586	4	0	0
T5	5830	0	0	0
T6	4526	14	0	0
T7	2623	5	0	0
T8	1765	0	0	0
T9	2433	4	0	0
T10	8517	6	0	0
T11	0	1	0	0
T12	0	37	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	1032	0	0
T2	6440	2	0	0
T3	38627	11	0	0
T4	3586	0	0	0
T5	5830	0	0	0
T6	4526	2	0	0
T7	2623	1	0	0
T8	1765	0	0	0
T9	2433	0	0	0
T10	8517	6	0	0
T11	3509	1	0	0
T14	0	1	0	0
T46	0	2	0	0
T50	0	1	0	0
T61	0	13	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49125464	11966	0	0
T1	159381	32	0	0
T2	25760	2	0	0
T3	154524	44	0	0
T4	14346	4	0	0
T5	23328	0	0	0
T6	18109	14	0	0
T7	10494	4	0	0
T8	7065	0	0	0
T9	9741	4	0	0
T10	34073	7	0	0
T11	0	1	0	0
T12	0	36	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49125464	948	0	0
T2	25760	2	0	0
T3	154524	13	0	0
T4	14346	0	0	0
T5	23328	0	0	0
T6	18109	0	0	0
T7	10494	0	0	0
T8	7065	0	0	0
T9	9741	0	0	0
T10	34073	7	0	0
T11	14037	1	0	0
T14	0	1	0	0
T46	0	2	0	0
T50	0	2	0	0
T61	0	12	0	0
T64	0	3	0	0
T67	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49125464	11966	0	0
T1	159381	32	0	0
T2	25760	2	0	0
T3	154524	44	0	0
T4	14346	4	0	0
T5	23328	0	0	0
T6	18109	14	0	0
T7	10494	4	0	0
T8	7065	0	0	0
T9	9741	4	0	0
T10	34073	7	0	0
T11	0	1	0	0
T12	0	36	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49125464	948	0	0
T2	25760	2	0	0
T3	154524	13	0	0
T4	14346	0	0	0
T5	23328	0	0	0
T6	18109	0	0	0
T7	10494	0	0	0
T8	7065	0	0	0
T9	9741	0	0	0
T10	34073	7	0	0
T11	14037	1	0	0
T14	0	1	0	0
T46	0	2	0	0
T50	0	2	0	0
T61	0	12	0	0
T64	0	3	0	0
T67	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563269	12019	0	0
T1	79688	32	0	0
T2	12880	3	0	0
T3	77265	39	0	0
T4	7173	4	0	0
T5	11657	0	0	0
T6	9054	14	0	0
T7	5245	4	0	0
T8	3532	0	0	0
T9	4868	4	0	0
T10	17038	6	0	0
T12	0	36	0	0
T13	0	67	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563269	942	0	0
T2	12880	3	0	0
T3	77265	6	0	0
T4	7173	0	0	0
T5	11657	0	0	0
T6	9054	0	0	0
T7	5245	0	0	0
T8	3532	0	0	0
T9	4868	0	0	0
T10	17038	6	0	0
T11	7018	1	0	0
T14	0	1	0	0
T46	0	4	0	0
T50	0	2	0	0
T61	0	14	0	0
T64	0	1	0	0
T67	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563269	12019	0	0
T1	79688	32	0	0
T2	12880	3	0	0
T3	77265	39	0	0
T4	7173	4	0	0
T5	11657	0	0	0
T6	9054	14	0	0
T7	5245	4	0	0
T8	3532	0	0	0
T9	4868	4	0	0
T10	17038	6	0	0
T12	0	36	0	0
T13	0	67	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563269	942	0	0
T2	12880	3	0	0
T3	77265	6	0	0
T4	7173	0	0	0
T5	11657	0	0	0
T6	9054	0	0	0
T7	5245	0	0	0
T8	3532	0	0	0
T9	4868	0	0	0
T10	17038	6	0	0
T11	7018	1	0	0
T14	0	1	0	0
T46	0	4	0	0
T50	0	2	0	0
T61	0	14	0	0
T64	0	1	0	0
T67	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563339	12061	0	0
T1	79683	32	0	0
T2	12881	4	0	0
T3	77262	44	0	0
T4	7170	4	0	0
T5	11668	0	0	0
T6	9054	14	0	0
T7	5245	5	0	0
T8	3532	0	0	0
T9	4866	4	0	0
T10	17037	9	0	0
T11	0	1	0	0
T12	0	36	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563339	959	0	0
T2	12881	4	0	0
T3	77262	12	0	0
T4	7170	0	0	0
T5	11668	0	0	0
T6	9054	0	0	0
T7	5245	1	0	0
T8	3532	0	0	0
T9	4866	0	0	0
T10	17037	9	0	0
T11	7020	1	0	0
T46	0	4	0	0
T50	0	3	0	0
T61	0	15	0	0
T70	0	22	0	0
T71	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563339	12061	0	0
T1	79683	32	0	0
T2	12881	4	0	0
T3	77262	44	0	0
T4	7170	4	0	0
T5	11668	0	0	0
T6	9054	14	0	0
T7	5245	5	0	0
T8	3532	0	0	0
T9	4866	4	0	0
T10	17037	9	0	0
T11	0	1	0	0
T12	0	36	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24563339	959	0	0
T2	12881	4	0	0
T3	77262	12	0	0
T4	7170	0	0	0
T5	11668	0	0	0
T6	9054	0	0	0
T7	5245	1	0	0
T8	3532	0	0	0
T9	4866	0	0	0
T10	17037	9	0	0
T11	7020	1	0	0
T46	0	4	0	0
T50	0	3	0	0
T61	0	15	0	0
T70	0	22	0	0
T71	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550633	20713	0	0
T1	5040	60	0	0
T2	804	6	0	0
T3	4889	60	0	0
T4	446	6	0	0
T5	731	3	0	0
T6	564	15	0	0
T7	326	6	0	0
T8	219	1	0	0
T9	303	5	0	0
T10	1063	10	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550633	978	0	0
T2	804	5	0	0
T3	4889	9	0	0
T4	446	0	0	0
T5	731	0	0	0
T6	564	0	0	0
T7	326	0	0	0
T8	219	0	0	0
T9	303	0	0	0
T10	1063	9	0	0
T11	439	3	0	0
T35	0	1	0	0
T46	0	5	0	0
T50	0	4	0	0
T61	0	14	0	0
T70	0	14	0	0
T71	0	7	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550633	20713	0	0
T1	5040	60	0	0
T2	804	6	0	0
T3	4889	60	0	0
T4	446	6	0	0
T5	731	3	0	0
T6	564	15	0	0
T7	326	6	0	0
T8	219	1	0	0
T9	303	5	0	0
T10	1063	10	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550633	978	0	0
T2	804	5	0	0
T3	4889	9	0	0
T4	446	0	0	0
T5	731	0	0	0
T6	564	0	0	0
T7	326	0	0	0
T8	219	0	0	0
T9	303	0	0	0
T10	1063	9	0	0
T11	439	3	0	0
T35	0	1	0	0
T46	0	5	0	0
T50	0	4	0	0
T61	0	14	0	0
T70	0	14	0	0
T71	0	7	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	13383	0	0
T1	39843	37	0	0
T2	6440	5	0	0
T3	38627	49	0	0
T4	3586	4	0	0
T5	5830	0	0	0
T6	4526	14	0	0
T7	2623	5	0	0
T8	1765	0	0	0
T9	2433	4	0	0
T10	8517	9	0	0
T11	0	1	0	0
T12	0	37	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	1075	0	0
T2	6440	5	0	0
T3	38627	12	0	0
T4	3586	0	0	0
T5	5830	0	0	0
T6	4526	0	0	0
T7	2623	1	0	0
T8	1765	0	0	0
T9	2433	0	0	0
T10	8517	9	0	0
T11	3509	2	0	0
T46	0	7	0	0
T50	0	5	0	0
T61	0	14	0	0
T70	0	15	0	0
T71	0	8	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	13383	0	0
T1	39843	37	0	0
T2	6440	5	0	0
T3	38627	49	0	0
T4	3586	4	0	0
T5	5830	0	0	0
T6	4526	14	0	0
T7	2623	5	0	0
T8	1765	0	0	0
T9	2433	4	0	0
T10	8517	9	0	0
T11	0	1	0	0
T12	0	37	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	1075	0	0
T2	6440	5	0	0
T3	38627	12	0	0
T4	3586	0	0	0
T5	5830	0	0	0
T6	4526	0	0	0
T7	2623	1	0	0
T8	1765	0	0	0
T9	2433	0	0	0
T10	8517	9	0	0
T11	3509	2	0	0
T46	0	7	0	0
T50	0	5	0	0
T61	0	14	0	0
T70	0	15	0	0
T71	0	8	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	13427	0	0
T1	39843	37	0	0
T2	6440	8	0	0
T3	38627	49	0	0
T4	3586	4	0	0
T5	5830	0	0	0
T6	4526	14	0	0
T7	2623	4	0	0
T8	1765	0	0	0
T9	2433	4	0	0
T10	8517	10	0	0
T11	0	2	0	0
T12	0	37	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	1124	0	0
T2	6440	8	0	0
T3	38627	14	0	0
T4	3586	0	0	0
T5	5830	0	0	0
T6	4526	0	0	0
T7	2623	0	0	0
T8	1765	0	0	0
T9	2433	0	0	0
T10	8517	10	0	0
T11	3509	3	0	0
T46	0	8	0	0
T50	0	7	0	0
T61	0	17	0	0
T70	0	17	0	0
T71	0	10	0	0
T93	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	13427	0	0
T1	39843	37	0	0
T2	6440	8	0	0
T3	38627	49	0	0
T4	3586	4	0	0
T5	5830	0	0	0
T6	4526	14	0	0
T7	2623	4	0	0
T8	1765	0	0	0
T9	2433	4	0	0
T10	8517	10	0	0
T11	0	2	0	0
T12	0	37	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	1124	0	0
T2	6440	8	0	0
T3	38627	14	0	0
T4	3586	0	0	0
T5	5830	0	0	0
T6	4526	0	0	0
T7	2623	0	0	0
T8	1765	0	0	0
T9	2433	0	0	0
T10	8517	10	0	0
T11	3509	3	0	0
T46	0	8	0	0
T50	0	7	0	0
T61	0	17	0	0
T70	0	17	0	0
T71	0	10	0	0
T93	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	13480	0	0
T1	39843	37	0	0
T2	6440	7	0	0
T3	38627	46	0	0
T4	3586	4	0	0
T5	5830	0	0	0
T6	4526	14	0	0
T7	2623	5	0	0
T8	1765	0	0	0
T9	2433	4	0	0
T10	8517	11	0	0
T11	0	2	0	0
T12	0	37	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	1170	0	0
T2	6440	7	0	0
T3	38627	10	0	0
T4	3586	0	0	0
T5	5830	0	0	0
T6	4526	0	0	0
T7	2623	1	0	0
T8	1765	0	0	0
T9	2433	0	0	0
T10	8517	11	0	0
T11	3509	2	0	0
T14	0	1	0	0
T46	0	8	0	0
T50	0	8	0	0
T60	0	1	0	0
T61	0	15	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	13480	0	0
T1	39843	37	0	0
T2	6440	7	0	0
T3	38627	46	0	0
T4	3586	4	0	0
T5	5830	0	0	0
T6	4526	14	0	0
T7	2623	5	0	0
T8	1765	0	0	0
T9	2433	4	0	0
T10	8517	11	0	0
T11	0	2	0	0
T12	0	37	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12281212	1170	0	0
T2	6440	7	0	0
T3	38627	10	0	0
T4	3586	0	0	0
T5	5830	0	0	0
T6	4526	0	0	0
T7	2623	1	0	0
T8	1765	0	0	0
T9	2433	0	0	0
T10	8517	11	0	0
T11	3509	2	0	0
T14	0	1	0	0
T46	0	8	0	0
T50	0	8	0	0
T60	0	1	0	0
T61	0	15	0	0