Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11699893	8054	0	0
alert_regwen_rd_A	11699893	2873	0	0
cpu_regwen_rd_A	11699893	2815	0	0
sw_rst_ctrl_n_0_rd_A	11699893	7841	0	0
sw_rst_ctrl_n_1_rd_A	11699893	8176	0	0
sw_rst_ctrl_n_2_rd_A	11699893	8230	0	0
sw_rst_ctrl_n_3_rd_A	11699893	8174	0	0
sw_rst_ctrl_n_4_rd_A	11699893	7816	0	0
sw_rst_ctrl_n_5_rd_A	11699893	8019	0	0
sw_rst_ctrl_n_6_rd_A	11699893	7936	0	0
sw_rst_ctrl_n_7_rd_A	11699893	7724	0	0
sw_rst_regwen_0_rd_A	11699893	3608	0	0
sw_rst_regwen_1_rd_A	11699893	3336	0	0
sw_rst_regwen_2_rd_A	11699893	3531	0	0
sw_rst_regwen_3_rd_A	11699893	3578	0	0
sw_rst_regwen_4_rd_A	11699893	3450	0	0
sw_rst_regwen_5_rd_A	11699893	3376	0	0
sw_rst_regwen_6_rd_A	11699893	3462	0	0
sw_rst_regwen_7_rd_A	11699893	3511	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	8054	0	0
T76	3720	55	0	0
T78	19301	3	0	0
T79	20287	5	0	0
T80	3674	602	0	0
T81	2709	5	0	0
T95	8099	347	0	0
T96	2998	40	0	0
T97	7359	140	0	0
T98	2704	30	0	0
T100	20603	4	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	2873	0	0
T38	25791	0	0	0
T68	34918	52	0	0
T69	42218	0	0	0
T70	84330	100	0	0
T71	3009	0	0	0
T104	0	143	0	0
T106	0	186	0	0
T107	0	30	0	0
T128	0	78	0	0
T129	0	114	0	0
T130	0	251	0	0
T131	0	116	0	0
T132	0	234	0	0
T133	26144	0	0	0
T134	3215	0	0	0
T135	5104	0	0	0
T136	5625	0	0	0
T137	5489	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	2815	0	0
T38	25791	0	0	0
T68	34918	48	0	0
T69	42218	0	0	0
T70	84330	83	0	0
T71	3009	0	0	0
T104	0	95	0	0
T106	0	207	0	0
T107	0	23	0	0
T128	0	75	0	0
T129	0	160	0	0
T130	0	256	0	0
T131	0	139	0	0
T132	0	187	0	0
T133	26144	0	0	0
T134	3215	0	0	0
T135	5104	0	0	0
T136	5625	0	0	0
T137	5489	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	7841	0	0
T14	5901	17	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	150	0	0
T59	36341	0	0	0
T60	5420	10	0	0
T67	0	8	0	0
T68	0	58	0	0
T70	0	302	0	0
T138	0	8	0	0
T139	0	15	0	0
T140	0	11	0	0
T141	0	15	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	8176	0	0
T14	5901	15	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	108	0	0
T59	36341	0	0	0
T60	5420	7	0	0
T67	0	16	0	0
T68	0	40	0	0
T70	0	359	0	0
T138	0	2	0	0
T139	0	4	0	0
T140	0	17	0	0
T141	0	17	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	8230	0	0
T14	5901	12	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	137	0	0
T59	36341	0	0	0
T60	5420	14	0	0
T67	0	4	0	0
T68	0	47	0	0
T70	0	415	0	0
T138	0	10	0	0
T139	0	14	0	0
T140	0	12	0	0
T141	0	8	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	8174	0	0
T14	5901	16	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	113	0	0
T59	36341	0	0	0
T60	5420	0	0	0
T67	0	15	0	0
T68	0	69	0	0
T70	0	339	0	0
T104	0	207	0	0
T138	0	7	0	0
T139	0	5	0	0
T140	0	27	0	0
T141	0	15	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	7816	0	0
T14	5901	24	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	126	0	0
T59	36341	0	0	0
T60	5420	5	0	0
T67	0	6	0	0
T68	0	46	0	0
T70	0	318	0	0
T138	0	12	0	0
T139	0	4	0	0
T140	0	17	0	0
T141	0	7	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	8019	0	0
T14	5901	10	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	130	0	0
T59	36341	0	0	0
T60	5420	6	0	0
T67	0	16	0	0
T68	0	40	0	0
T70	0	332	0	0
T104	0	242	0	0
T138	0	8	0	0
T139	0	1	0	0
T140	0	3	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	7936	0	0
T14	5901	7	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	103	0	0
T59	36341	0	0	0
T60	5420	6	0	0
T67	0	10	0	0
T68	0	57	0	0
T70	0	339	0	0
T138	0	13	0	0
T139	0	15	0	0
T140	0	5	0	0
T141	0	18	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	7724	0	0
T14	5901	12	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	119	0	0
T59	36341	0	0	0
T60	5420	8	0	0
T67	0	14	0	0
T68	0	59	0	0
T70	0	333	0	0
T138	0	24	0	0
T139	0	5	0	0
T140	0	15	0	0
T141	0	1	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	3608	0	0
T14	5901	13	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	33	0	0
T59	36341	0	0	0
T60	5420	6	0	0
T67	0	9	0	0
T68	0	42	0	0
T70	0	75	0	0
T104	0	156	0	0
T139	0	3	0	0
T140	0	7	0	0
T141	0	7	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	3336	0	0
T14	5901	3	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	17	0	0
T59	36341	0	0	0
T60	5420	1	0	0
T67	0	2	0	0
T68	0	54	0	0
T70	0	75	0	0
T104	0	129	0	0
T139	0	4	0	0
T141	0	13	0	0
T142	0	21	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	3531	0	0
T14	5901	6	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	22	0	0
T59	36341	0	0	0
T60	5420	0	0	0
T67	0	1	0	0
T68	0	58	0	0
T70	0	69	0	0
T104	0	145	0	0
T140	0	3	0	0
T142	0	14	0	0
T143	0	4	0	0
T144	0	41	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	3578	0	0
T14	5901	6	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	17	0	0
T59	36341	0	0	0
T60	5420	0	0	0
T67	0	7	0	0
T68	0	71	0	0
T70	0	116	0	0
T104	0	131	0	0
T139	0	8	0	0
T140	0	7	0	0
T142	0	26	0	0
T143	0	7	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	3450	0	0
T14	5901	3	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	34	0	0
T59	36341	0	0	0
T60	5420	10	0	0
T67	0	4	0	0
T68	0	33	0	0
T70	0	95	0	0
T104	0	144	0	0
T140	0	8	0	0
T141	0	2	0	0
T142	0	36	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	3376	0	0
T14	5901	10	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	23	0	0
T59	36341	0	0	0
T60	5420	6	0	0
T67	0	2	0	0
T68	0	42	0	0
T70	0	77	0	0
T104	0	118	0	0
T140	0	12	0	0
T141	0	2	0	0
T142	0	36	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	3462	0	0
T14	5901	5	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	36	0	0
T59	36341	0	0	0
T60	5420	0	0	0
T67	0	7	0	0
T68	0	47	0	0
T70	0	100	0	0
T104	0	119	0	0
T139	0	9	0	0
T140	0	7	0	0
T141	0	6	0	0
T142	0	15	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11699893	3511	0	0
T14	5901	7	0	0
T15	26218	0	0	0
T37	53530	0	0	0
T46	6616	0	0	0
T47	16617	0	0	0
T48	2008	0	0	0
T49	5489	0	0	0
T50	8242	20	0	0
T59	36341	0	0	0
T60	5420	5	0	0
T67	0	9	0	0
T68	0	38	0	0
T70	0	100	0	0
T104	0	132	0	0
T139	0	6	0	0
T140	0	5	0	0
T141	0	10	0	0