Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	626501	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

376651

1

T1

4611

T2

7478

T3

6505

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	534860	1			T1	7060		T2	11008		T3	9759
values[0x0]	233876	1			T1	2666		T2	4458		T3	4054
values[0x1]	234416	1			T1	2738		T2	4514		T3	3996

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	525925	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

477227

1

T1

5890

T2

9520

T3

8253

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3623	1			T1	42		T2	94		T3	70
valid_sources[0x01]	4101	1			T1	45		T2	101		T3	47
valid_sources[0x02]	3667	1			T1	50		T2	65		T3	83
valid_sources[0x03]	3465	1			T1	50		T2	76		T3	92
valid_sources[0x04]	3181	1			T1	47		T2	60		T3	102
valid_sources[0x05]	3475	1			T1	63		T2	104		T3	76
valid_sources[0x06]	3819	1			T1	76		T2	60		T3	75
valid_sources[0x07]	3670	1			T1	31		T2	82		T3	55
valid_sources[0x08]	3092	1			T1	49		T2	68		T3	58
valid_sources[0x09]	3542	1			T1	45		T2	70		T3	49
valid_sources[0x0a]	3616	1			T1	36		T2	114		T3	73
valid_sources[0x0b]	3367	1			T1	35		T2	48		T3	65
valid_sources[0x0c]	4072	1			T1	56		T2	96		T3	65
valid_sources[0x0d]	3589	1			T1	38		T2	93		T3	55
valid_sources[0x0e]	3512	1			T1	94		T2	67		T3	66
valid_sources[0x0f]	4243	1			T1	64		T2	76		T3	104
valid_sources[0x10]	3329	1			T1	40		T2	82		T3	74
valid_sources[0x11]	6769	1			T1	36		T2	53		T3	60
valid_sources[0x12]	4115	1			T1	33		T2	50		T3	63
valid_sources[0x13]	4575	1			T1	63		T2	68		T3	46
valid_sources[0x14]	3284	1			T1	81		T2	69		T3	91
valid_sources[0x15]	3379	1			T1	61		T2	98		T3	80
valid_sources[0x16]	3376	1			T1	52		T2	82		T3	59
valid_sources[0x17]	5751	1			T1	55		T2	75		T3	61
valid_sources[0x18]	3260	1			T1	27		T2	86		T3	69
valid_sources[0x19]	3374	1			T1	12		T2	112		T3	67
valid_sources[0x1a]	4099	1			T1	28		T2	92		T3	56
valid_sources[0x1b]	3312	1			T1	88		T2	53		T3	91
valid_sources[0x1c]	3639	1			T1	33		T2	68		T3	82
valid_sources[0x1d]	3477	1			T1	57		T2	49		T3	26
valid_sources[0x1e]	3400	1			T1	59		T2	94		T3	87
valid_sources[0x1f]	3875	1			T1	68		T2	114		T3	48
valid_sources[0x20]	3100	1			T1	43		T2	89		T3	76
valid_sources[0x21]	3859	1			T1	39		T2	68		T3	82
valid_sources[0x22]	3849	1			T1	77		T2	86		T3	64
valid_sources[0x23]	4373	1			T1	30		T2	88		T3	73
valid_sources[0x24]	3159	1			T1	27		T2	40		T3	71
valid_sources[0x25]	7267	1			T1	68		T2	71		T3	70
valid_sources[0x26]	3120	1			T1	60		T2	108		T3	68
valid_sources[0x27]	7479	1			T1	32		T2	94		T3	70
valid_sources[0x28]	3445	1			T1	61		T2	67		T3	66
valid_sources[0x29]	3201	1			T1	25		T2	28		T3	93
valid_sources[0x2a]	3607	1			T1	53		T2	109		T3	77
valid_sources[0x2b]	3294	1			T1	59		T2	107		T3	99
valid_sources[0x2c]	3034	1			T1	74		T2	54		T3	58
valid_sources[0x2d]	3760	1			T1	44		T2	46		T3	73
valid_sources[0x2e]	3306	1			T1	39		T2	107		T3	66
valid_sources[0x2f]	6842	1			T1	35		T2	96		T3	65
valid_sources[0x30]	3981	1			T1	31		T2	106		T3	72
valid_sources[0x31]	3822	1			T1	42		T2	78		T3	65
valid_sources[0x32]	3722	1			T1	27		T2	54		T3	48
valid_sources[0x33]	5102	1			T1	72		T2	78		T3	62
valid_sources[0x34]	3339	1			T1	55		T2	119		T3	74
valid_sources[0x35]	3066	1			T1	23		T2	74		T3	79
valid_sources[0x36]	3567	1			T1	63		T2	75		T3	63
valid_sources[0x37]	3166	1			T1	61		T2	79		T3	69
valid_sources[0x38]	7194	1			T1	57		T2	92		T3	55
valid_sources[0x39]	3520	1			T1	61		T2	70		T3	36
valid_sources[0x3a]	4180	1			T1	53		T2	75		T3	60
valid_sources[0x3b]	3942	1			T1	45		T2	60		T3	45
valid_sources[0x3c]	3512	1			T1	51		T2	45		T3	52
valid_sources[0x3d]	3320	1			T1	27		T2	79		T3	99
valid_sources[0x3e]	3325	1			T1	59		T2	55		T3	72
valid_sources[0x3f]	3527	1			T1	80		T2	109		T3	91
valid_sources[0x40]	4136	1			T1	96		T2	90		T3	60
valid_sources[0x41]	3840	1			T1	37		T2	69		T3	27
valid_sources[0x42]	3587	1			T1	46		T2	56		T3	94
valid_sources[0x43]	3306	1			T1	103		T2	99		T3	78
valid_sources[0x44]	3639	1			T1	87		T2	68		T3	87
valid_sources[0x45]	3137	1			T1	41		T2	44		T3	88
valid_sources[0x46]	3348	1			T1	33		T2	68		T3	79
valid_sources[0x47]	3991	1			T1	50		T2	65		T3	75
valid_sources[0x48]	3497	1			T1	80		T2	68		T3	53
valid_sources[0x49]	6677	1			T1	36		T2	98		T3	47
valid_sources[0x4a]	4369	1			T1	28		T2	70		T3	54
valid_sources[0x4b]	4263	1			T1	60		T2	46		T3	105
valid_sources[0x4c]	4032	1			T1	49		T2	82		T3	44
valid_sources[0x4d]	3798	1			T1	46		T2	80		T3	89
valid_sources[0x4e]	3587	1			T1	36		T2	46		T3	71
valid_sources[0x4f]	3653	1			T1	34		T2	76		T3	64
valid_sources[0x50]	3946	1			T1	64		T2	49		T3	104
valid_sources[0x51]	3380	1			T1	27		T2	87		T3	108
valid_sources[0x52]	2937	1			T1	50		T2	102		T3	49
valid_sources[0x53]	3991	1			T1	52		T2	108		T3	80
valid_sources[0x54]	4303	1			T1	34		T2	63		T3	74
valid_sources[0x55]	4591	1			T1	16		T2	70		T3	103
valid_sources[0x56]	3951	1			T1	35		T2	71		T3	77
valid_sources[0x57]	3460	1			T1	35		T2	79		T3	89
valid_sources[0x58]	3307	1			T1	50		T2	81		T3	53
valid_sources[0x59]	4181	1			T1	40		T2	73		T3	52
valid_sources[0x5a]	2920	1			T1	39		T2	52		T3	105
valid_sources[0x5b]	3809	1			T1	40		T2	61		T3	61
valid_sources[0x5c]	3243	1			T1	27		T2	108		T3	58
valid_sources[0x5d]	4218	1			T1	19		T2	60		T3	69
valid_sources[0x5e]	3560	1			T1	43		T2	81		T3	39
valid_sources[0x5f]	4997	1			T1	51		T2	57		T3	85
valid_sources[0x60]	4221	1			T1	69		T2	76		T3	36
valid_sources[0x61]	4944	1			T1	74		T2	96		T3	71
valid_sources[0x62]	3567	1			T1	25		T2	120		T3	68
valid_sources[0x63]	3661	1			T1	46		T2	81		T3	101
valid_sources[0x64]	3027	1			T1	21		T2	80		T3	57
valid_sources[0x65]	3432	1			T1	44		T2	98		T3	88
valid_sources[0x66]	4034	1			T1	43		T2	63		T3	92
valid_sources[0x67]	3595	1			T1	23		T2	98		T3	44
valid_sources[0x68]	3225	1			T1	80		T2	55		T3	99
valid_sources[0x69]	3317	1			T1	73		T2	76		T3	53
valid_sources[0x6a]	3487	1			T1	54		T2	90		T3	128
valid_sources[0x6b]	3478	1			T1	13		T2	99		T3	57
valid_sources[0x6c]	3339	1			T1	29		T2	80		T3	72
valid_sources[0x6d]	4042	1			T1	44		T2	99		T3	75
valid_sources[0x6e]	3576	1			T1	46		T2	87		T3	69
valid_sources[0x6f]	4009	1			T1	59		T2	98		T3	51
valid_sources[0x70]	5003	1			T1	31		T2	97		T3	44
valid_sources[0x71]	4005	1			T1	61		T2	116		T3	115
valid_sources[0x72]	3171	1			T1	60		T2	76		T3	72
valid_sources[0x73]	3436	1			T1	66		T2	67		T3	50
valid_sources[0x74]	3166	1			T1	41		T2	71		T3	94
valid_sources[0x75]	3442	1			T1	104		T2	90		T3	108
valid_sources[0x76]	3547	1			T1	56		T2	82		T3	96
valid_sources[0x77]	5183	1			T1	45		T2	99		T3	44
valid_sources[0x78]	3595	1			T1	37		T2	71		T3	118
valid_sources[0x79]	3668	1			T1	51		T2	72		T3	64
valid_sources[0x7a]	3304	1			T1	39		T2	37		T3	91
valid_sources[0x7b]	4022	1			T1	53		T2	60		T3	70
valid_sources[0x7c]	3578	1			T1	11		T2	88		T3	71
valid_sources[0x7d]	3903	1			T1	69		T2	92		T3	84
valid_sources[0x7e]	3826	1			T1	24		T2	77		T3	42
valid_sources[0x7f]	4676	1			T1	25		T2	67		T3	66
valid_sources[0x80]	5517	1			T1	46		T2	55		T3	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

250666

1

T1

3290

T2

5171

T3

4567

values[0x0]

all_enables

biggest_size

81868

1

T1

857

T2

1535

T3

1287

values[0x1]

all_enables

biggest_size

44117

1

T1

464

T2

772

T3

651