Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56705568	9264	0	0
CascadeEffAonToRstPorAboveRise_A	56705568	9264	0	0
CascadeEffAonToRstPorIoAboveFall_A	54435480	9264	0	0
CascadeEffAonToRstPorIoAboveRise_A	54435480	9264	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27218644	9264	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27218644	9264	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13609035	9264	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13609035	9264	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27218733	9264	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27218733	9264	0	0
CascadeLcToLcAboveFall_A	56705568	22750	0	0
CascadeLcToLcAboveRise_A	56705568	22750	0	0
CascadeLcToLcAonAboveFall_A	1718245	22750	0	0
CascadeLcToLcAonAboveRise_A	1718245	22750	0	0
CascadeLcToLcShadowedAboveFall_A	56705568	22750	0	0
CascadeLcToLcShadowedAboveRise_A	56705568	22750	0	0
CascadePorToAonAboveFall_A	1718245	7342	0	0
CascadeSysToSysAboveFall_A	56705568	22750	0	0
CascadeSysToSysAboveRise_A	56705568	22750	0	0
ScanRstToAonRise_A	1718245	206	0	0
StablePorToAonRise_A	1718245	9264	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12076893	22750	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12076893	22750	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12076893	22750	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12076893	22750	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13609035	22750	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13609035	22750	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12076893	22750	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12076893	22750	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12076893	22750	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12076893	22750	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56705568	9264	0	0
T1	671980	93	0	0
T2	103928	125	0	0
T3	936158	114	0	0
T4	23917	1	0	0
T5	7288	1	0	0
T6	128401	17	0	0
T7	24352	8	0	0
T8	7859	1	0	0
T9	24283	8	0	0
T10	121922	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56705568	9264	0	0
T1	671980	93	0	0
T2	103928	125	0	0
T3	936158	114	0	0
T4	23917	1	0	0
T5	7288	1	0	0
T6	128401	17	0	0
T7	24352	8	0	0
T8	7859	1	0	0
T9	24283	8	0	0
T10	121922	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54435480	9264	0	0
T1	645138	93	0	0
T2	997637	125	0	0
T3	898659	114	0	0
T4	22959	1	0	0
T5	6995	1	0	0
T6	123256	17	0	0
T7	23388	8	0	0
T8	7545	1	0	0
T9	23306	8	0	0
T10	117025	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54435480	9264	0	0
T1	645138	93	0	0
T2	997637	125	0	0
T3	898659	114	0	0
T4	22959	1	0	0
T5	6995	1	0	0
T6	123256	17	0	0
T7	23388	8	0	0
T8	7545	1	0	0
T9	23306	8	0	0
T10	117025	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218644	9264	0	0
T1	322582	93	0	0
T2	498886	125	0	0
T3	449348	114	0	0
T4	11480	1	0	0
T5	3497	1	0	0
T6	61632	17	0	0
T7	11692	8	0	0
T8	3773	1	0	0
T9	11653	8	0	0
T10	58517	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218644	9264	0	0
T1	322582	93	0	0
T2	498886	125	0	0
T3	449348	114	0	0
T4	11480	1	0	0
T5	3497	1	0	0
T6	61632	17	0	0
T7	11692	8	0	0
T8	3773	1	0	0
T9	11653	8	0	0
T10	58517	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	9264	0	0
T1	161275	93	0	0
T2	249429	125	0	0
T3	224670	114	0	0
T4	5739	1	0	0
T5	1748	1	0	0
T6	30812	17	0	0
T7	5849	8	0	0
T8	1885	1	0	0
T9	5826	8	0	0
T10	29259	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	9264	0	0
T1	161275	93	0	0
T2	249429	125	0	0
T3	224670	114	0	0
T4	5739	1	0	0
T5	1748	1	0	0
T6	30812	17	0	0
T7	5849	8	0	0
T8	1885	1	0	0
T9	5826	8	0	0
T10	29259	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218733	9264	0	0
T1	322594	93	0	0
T2	498847	125	0	0
T3	449332	114	0	0
T4	11479	1	0	0
T5	3497	1	0	0
T6	61628	17	0	0
T7	11693	8	0	0
T8	3772	1	0	0
T9	11654	8	0	0
T10	58515	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218733	9264	0	0
T1	322594	93	0	0
T2	498847	125	0	0
T3	449332	114	0	0
T4	11479	1	0	0
T5	3497	1	0	0
T6	61628	17	0	0
T7	11693	8	0	0
T8	3772	1	0	0
T9	11654	8	0	0
T10	58515	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56705568	22750	0	0
T1	671980	240	0	0
T2	103928	380	0	0
T3	936158	356	0	0
T4	23917	17	0	0
T5	7288	1	0	0
T6	128401	48	0	0
T7	24352	8	0	0
T8	7859	1	0	0
T9	24283	8	0	0
T10	121922	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56705568	22750	0	0
T1	671980	240	0	0
T2	103928	380	0	0
T3	936158	356	0	0
T4	23917	17	0	0
T5	7288	1	0	0
T6	128401	48	0	0
T7	24352	8	0	0
T8	7859	1	0	0
T9	24283	8	0	0
T10	121922	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1718245	22750	0	0
T1	20487	240	0	0
T2	31560	380	0	0
T3	28567	356	0	0
T4	716	17	0	0
T5	217	1	0	0
T6	3895	48	0	0
T7	732	8	0	0
T8	234	1	0	0
T9	729	8	0	0
T10	3671	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1718245	22750	0	0
T1	20487	240	0	0
T2	31560	380	0	0
T3	28567	356	0	0
T4	716	17	0	0
T5	217	1	0	0
T6	3895	48	0	0
T7	732	8	0	0
T8	234	1	0	0
T9	729	8	0	0
T10	3671	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56705568	22750	0	0
T1	671980	240	0	0
T2	103928	380	0	0
T3	936158	356	0	0
T4	23917	17	0	0
T5	7288	1	0	0
T6	128401	48	0	0
T7	24352	8	0	0
T8	7859	1	0	0
T9	24283	8	0	0
T10	121922	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56705568	22750	0	0
T1	671980	240	0	0
T2	103928	380	0	0
T3	936158	356	0	0
T4	23917	17	0	0
T5	7288	1	0	0
T6	128401	48	0	0
T7	24352	8	0	0
T8	7859	1	0	0
T9	24283	8	0	0
T10	121922	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1718245	7342	0	0
T1	20487	50	0	0
T2	31560	66	0	0
T3	28567	58	0	0
T4	716	1	0	0
T5	217	1	0	0
T6	3895	8	0	0
T7	732	8	0	0
T8	234	1	0	0
T9	729	8	0	0
T10	3671	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56705568	22750	0	0
T1	671980	240	0	0
T2	103928	380	0	0
T3	936158	356	0	0
T4	23917	17	0	0
T5	7288	1	0	0
T6	128401	48	0	0
T7	24352	8	0	0
T8	7859	1	0	0
T9	24283	8	0	0
T10	121922	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56705568	22750	0	0
T1	671980	240	0	0
T2	103928	380	0	0
T3	936158	356	0	0
T4	23917	17	0	0
T5	7288	1	0	0
T6	128401	48	0	0
T7	24352	8	0	0
T8	7859	1	0	0
T9	24283	8	0	0
T10	121922	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1718245	206	0	0
T1	20487	3	0	0
T2	31560	1	0	0
T3	28567	6	0	0
T4	716	0	0	0
T5	217	0	0	0
T6	3895	1	0	0
T7	732	0	0	0
T8	234	0	0	0
T9	729	0	0	0
T10	3671	0	0	0
T28	0	5	0	0
T43	0	4	0	0
T80	0	2	0	0
T88	0	2	0	0
T90	0	4	0	0
T128	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1718245	9264	0	0
T1	20487	93	0	0
T2	31560	125	0	0
T3	28567	114	0	0
T4	716	1	0	0
T5	217	1	0	0
T6	3895	17	0	0
T7	732	8	0	0
T8	234	1	0	0
T9	729	8	0	0
T10	3671	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12076893	22750	0	0
T1	140729	240	0	0
T2	216711	380	0	0
T3	195357	356	0	0
T4	4575	17	0	0
T5	1729	1	0	0
T6	26083	48	0	0
T7	5684	8	0	0
T8	1795	1	0	0
T9	5089	8	0	0
T10	26249	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12076893	22750	0	0
T1	140729	240	0	0
T2	216711	380	0	0
T3	195357	356	0	0
T4	4575	17	0	0
T5	1729	1	0	0
T6	26083	48	0	0
T7	5684	8	0	0
T8	1795	1	0	0
T9	5089	8	0	0
T10	26249	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12076893	22750	0	0
T1	140729	240	0	0
T2	216711	380	0	0
T3	195357	356	0	0
T4	4575	17	0	0
T5	1729	1	0	0
T6	26083	48	0	0
T7	5684	8	0	0
T8	1795	1	0	0
T9	5089	8	0	0
T10	26249	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12076893	22750	0	0
T1	140729	240	0	0
T2	216711	380	0	0
T3	195357	356	0	0
T4	4575	17	0	0
T5	1729	1	0	0
T6	26083	48	0	0
T7	5684	8	0	0
T8	1795	1	0	0
T9	5089	8	0	0
T10	26249	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	22750	0	0
T1	161275	240	0	0
T2	249429	380	0	0
T3	224670	356	0	0
T4	5739	17	0	0
T5	1748	1	0	0
T6	30812	48	0	0
T7	5849	8	0	0
T8	1885	1	0	0
T9	5826	8	0	0
T10	29259	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	22750	0	0
T1	161275	240	0	0
T2	249429	380	0	0
T3	224670	356	0	0
T4	5739	17	0	0
T5	1748	1	0	0
T6	30812	48	0	0
T7	5849	8	0	0
T8	1885	1	0	0
T9	5826	8	0	0
T10	29259	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12076893	22750	0	0
T1	140729	240	0	0
T2	216711	380	0	0
T3	195357	356	0	0
T4	4575	17	0	0
T5	1729	1	0	0
T6	26083	48	0	0
T7	5684	8	0	0
T8	1795	1	0	0
T9	5089	8	0	0
T10	26249	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12076893	22750	0	0
T1	140729	240	0	0
T2	216711	380	0	0
T3	195357	356	0	0
T4	4575	17	0	0
T5	1729	1	0	0
T6	26083	48	0	0
T7	5684	8	0	0
T8	1795	1	0	0
T9	5089	8	0	0
T10	26249	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12076893	22750	0	0
T1	140729	240	0	0
T2	216711	380	0	0
T3	195357	356	0	0
T4	4575	17	0	0
T5	1729	1	0	0
T6	26083	48	0	0
T7	5684	8	0	0
T8	1795	1	0	0
T9	5089	8	0	0
T10	26249	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12076893	22750	0	0
T1	140729	240	0	0
T2	216711	380	0	0
T3	195357	356	0	0
T4	4575	17	0	0
T5	1729	1	0	0
T6	26083	48	0	0
T7	5684	8	0	0
T8	1795	1	0	0
T9	5089	8	0	0
T10	26249	102	0	0