Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13609035	14337	0	0
gen_assertions[0].RstEnOn_A	13609035	1035	0	0
gen_assertions[0].RstNOff_A	13609035	14337	0	0
gen_assertions[0].RstNOn_A	13609035	1035	0	0
gen_assertions[1].RstEnOff_A	54435480	13057	0	0
gen_assertions[1].RstEnOn_A	54435480	1033	0	0
gen_assertions[1].RstNOff_A	54435480	13057	0	0
gen_assertions[1].RstNOn_A	54435480	1033	0	0
gen_assertions[2].RstEnOff_A	27218644	13100	0	0
gen_assertions[2].RstEnOn_A	27218644	1000	0	0
gen_assertions[2].RstNOff_A	27218644	13100	0	0
gen_assertions[2].RstNOn_A	27218644	1000	0	0
gen_assertions[3].RstEnOff_A	27218733	13158	0	0
gen_assertions[3].RstEnOn_A	27218733	1058	0	0
gen_assertions[3].RstNOff_A	27218733	13158	0	0
gen_assertions[3].RstNOn_A	27218733	1058	0	0
gen_assertions[4].RstEnOff_A	1718245	22562	0	0
gen_assertions[4].RstEnOn_A	1718245	1088	0	0
gen_assertions[4].RstNOff_A	1718245	22562	0	0
gen_assertions[4].RstNOn_A	1718245	1088	0	0
gen_assertions[5].RstEnOff_A	13609035	14609	0	0
gen_assertions[5].RstEnOn_A	13609035	1156	0	0
gen_assertions[5].RstNOff_A	13609035	14609	0	0
gen_assertions[5].RstNOn_A	13609035	1156	0	0
gen_assertions[6].RstEnOff_A	13609035	14640	0	0
gen_assertions[6].RstEnOn_A	13609035	1178	0	0
gen_assertions[6].RstNOff_A	13609035	14640	0	0
gen_assertions[6].RstNOn_A	13609035	1178	0	0
gen_assertions[7].RstEnOff_A	13609035	14697	0	0
gen_assertions[7].RstEnOn_A	13609035	1240	0	0
gen_assertions[7].RstNOff_A	13609035	14697	0	0
gen_assertions[7].RstNOn_A	13609035	1240	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	14337	0	0
T1	161275	154	0	0
T2	249429	276	0	0
T3	224670	251	0	0
T4	5739	16	0	0
T5	1748	0	0	0
T6	30812	31	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	75	0	0
T11	0	4	0	0
T12	0	35	0	0
T13	0	5	0	0
T14	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	1035	0	0
T1	161275	8	0	0
T2	249429	22	0	0
T3	224670	10	0	0
T4	5739	1	0	0
T5	1748	0	0	0
T6	30812	0	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	0	0	0
T11	0	4	0	0
T13	0	1	0	0
T28	0	27	0	0
T29	0	6	0	0
T32	0	7	0	0
T43	0	40	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	14337	0	0
T1	161275	154	0	0
T2	249429	276	0	0
T3	224670	251	0	0
T4	5739	16	0	0
T5	1748	0	0	0
T6	30812	31	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	75	0	0
T11	0	4	0	0
T12	0	35	0	0
T13	0	5	0	0
T14	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	1035	0	0
T1	161275	8	0	0
T2	249429	22	0	0
T3	224670	10	0	0
T4	5739	1	0	0
T5	1748	0	0	0
T6	30812	0	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	0	0	0
T11	0	4	0	0
T13	0	1	0	0
T28	0	27	0	0
T29	0	6	0	0
T32	0	7	0	0
T43	0	40	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54435480	13057	0	0
T1	645138	133	0	0
T2	997637	250	0	0
T3	898659	215	0	0
T4	22959	14	0	0
T5	6995	0	0	0
T6	123256	27	0	0
T7	23388	0	0	0
T8	7545	0	0	0
T9	23306	0	0	0
T10	117025	73	0	0
T11	0	3	0	0
T12	0	31	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54435480	1033	0	0
T1	645138	8	0	0
T2	997637	22	0	0
T3	898659	11	0	0
T4	22959	0	0	0
T5	6995	0	0	0
T6	123256	0	0	0
T7	23388	0	0	0
T8	7545	0	0	0
T9	23306	0	0	0
T10	117025	0	0	0
T11	0	3	0	0
T28	0	30	0	0
T29	0	8	0	0
T34	0	3	0	0
T43	0	42	0	0
T52	0	6	0	0
T78	0	2	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54435480	13057	0	0
T1	645138	133	0	0
T2	997637	250	0	0
T3	898659	215	0	0
T4	22959	14	0	0
T5	6995	0	0	0
T6	123256	27	0	0
T7	23388	0	0	0
T8	7545	0	0	0
T9	23306	0	0	0
T10	117025	73	0	0
T11	0	3	0	0
T12	0	31	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54435480	1033	0	0
T1	645138	8	0	0
T2	997637	22	0	0
T3	898659	11	0	0
T4	22959	0	0	0
T5	6995	0	0	0
T6	123256	0	0	0
T7	23388	0	0	0
T8	7545	0	0	0
T9	23306	0	0	0
T10	117025	0	0	0
T11	0	3	0	0
T28	0	30	0	0
T29	0	8	0	0
T34	0	3	0	0
T43	0	42	0	0
T52	0	6	0	0
T78	0	2	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218644	13100	0	0
T1	322582	132	0	0
T2	498886	251	0	0
T3	449348	215	0	0
T4	11480	14	0	0
T5	3497	0	0	0
T6	61632	27	0	0
T7	11692	0	0	0
T8	3773	0	0	0
T9	11653	0	0	0
T10	58517	73	0	0
T11	0	7	0	0
T12	0	31	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218644	1000	0	0
T1	322582	7	0	0
T2	498886	22	0	0
T3	449348	10	0	0
T4	11480	0	0	0
T5	3497	0	0	0
T6	61632	0	0	0
T7	11692	0	0	0
T8	3773	0	0	0
T9	11653	0	0	0
T10	58517	0	0	0
T11	0	7	0	0
T28	0	28	0	0
T29	0	11	0	0
T32	0	1	0	0
T33	0	1	0	0
T43	0	40	0	0
T79	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218644	13100	0	0
T1	322582	132	0	0
T2	498886	251	0	0
T3	449348	215	0	0
T4	11480	14	0	0
T5	3497	0	0	0
T6	61632	27	0	0
T7	11692	0	0	0
T8	3773	0	0	0
T9	11653	0	0	0
T10	58517	73	0	0
T11	0	7	0	0
T12	0	31	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218644	1000	0	0
T1	322582	7	0	0
T2	498886	22	0	0
T3	449348	10	0	0
T4	11480	0	0	0
T5	3497	0	0	0
T6	61632	0	0	0
T7	11692	0	0	0
T8	3773	0	0	0
T9	11653	0	0	0
T10	58517	0	0	0
T11	0	7	0	0
T28	0	28	0	0
T29	0	11	0	0
T32	0	1	0	0
T33	0	1	0	0
T43	0	40	0	0
T79	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218733	13158	0	0
T1	322594	131	0	0
T2	498847	250	0	0
T3	449332	215	0	0
T4	11479	14	0	0
T5	3497	0	0	0
T6	61628	27	0	0
T7	11693	0	0	0
T8	3772	0	0	0
T9	11654	0	0	0
T10	58515	73	0	0
T11	0	7	0	0
T12	0	31	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218733	1058	0	0
T1	322594	5	0	0
T2	498847	21	0	0
T3	449332	10	0	0
T4	11479	0	0	0
T5	3497	0	0	0
T6	61628	0	0	0
T7	11693	0	0	0
T8	3772	0	0	0
T9	11654	0	0	0
T10	58515	0	0	0
T11	0	7	0	0
T28	0	28	0	0
T29	0	8	0	0
T43	0	47	0	0
T52	0	8	0	0
T78	0	5	0	0
T80	0	7	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218733	13158	0	0
T1	322594	131	0	0
T2	498847	250	0	0
T3	449332	215	0	0
T4	11479	14	0	0
T5	3497	0	0	0
T6	61628	27	0	0
T7	11693	0	0	0
T8	3772	0	0	0
T9	11654	0	0	0
T10	58515	73	0	0
T11	0	7	0	0
T12	0	31	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27218733	1058	0	0
T1	322594	5	0	0
T2	498847	21	0	0
T3	449332	10	0	0
T4	11479	0	0	0
T5	3497	0	0	0
T6	61628	0	0	0
T7	11693	0	0	0
T8	3772	0	0	0
T9	11654	0	0	0
T10	58515	0	0	0
T11	0	7	0	0
T28	0	28	0	0
T29	0	8	0	0
T43	0	47	0	0
T52	0	8	0	0
T78	0	5	0	0
T80	0	7	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1718245	22562	0	0
T1	20487	243	0	0
T2	31560	390	0	0
T3	28567	359	0	0
T4	716	17	0	0
T5	217	1	0	0
T6	3895	48	0	0
T7	732	3	0	0
T8	234	1	0	0
T9	729	3	0	0
T10	3671	76	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1718245	1088	0	0
T1	20487	8	0	0
T2	31560	20	0	0
T3	28567	8	0	0
T4	716	0	0	0
T5	217	0	0	0
T6	3895	0	0	0
T7	732	0	0	0
T8	234	0	0	0
T9	729	0	0	0
T10	3671	0	0	0
T11	0	10	0	0
T28	0	29	0	0
T29	0	9	0	0
T43	0	44	0	0
T52	0	10	0	0
T78	0	5	0	0
T81	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1718245	22562	0	0
T1	20487	243	0	0
T2	31560	390	0	0
T3	28567	359	0	0
T4	716	17	0	0
T5	217	1	0	0
T6	3895	48	0	0
T7	732	3	0	0
T8	234	1	0	0
T9	729	3	0	0
T10	3671	76	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1718245	1088	0	0
T1	20487	8	0	0
T2	31560	20	0	0
T3	28567	8	0	0
T4	716	0	0	0
T5	217	0	0	0
T6	3895	0	0	0
T7	732	0	0	0
T8	234	0	0	0
T9	729	0	0	0
T10	3671	0	0	0
T11	0	10	0	0
T28	0	29	0	0
T29	0	9	0	0
T43	0	44	0	0
T52	0	10	0	0
T78	0	5	0	0
T81	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	14609	0	0
T1	161275	154	0	0
T2	249429	277	0	0
T3	224670	250	0	0
T4	5739	16	0	0
T5	1748	0	0	0
T6	30812	31	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	75	0	0
T11	0	9	0	0
T12	0	35	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	1156	0	0
T1	161275	8	0	0
T2	249429	23	0	0
T3	224670	8	0	0
T4	5739	0	0	0
T5	1748	0	0	0
T6	30812	0	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	0	0	0
T11	0	9	0	0
T28	0	27	0	0
T29	0	12	0	0
T43	0	44	0	0
T52	0	9	0	0
T78	0	7	0	0
T82	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	14609	0	0
T1	161275	154	0	0
T2	249429	277	0	0
T3	224670	250	0	0
T4	5739	16	0	0
T5	1748	0	0	0
T6	30812	31	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	75	0	0
T11	0	9	0	0
T12	0	35	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	1156	0	0
T1	161275	8	0	0
T2	249429	23	0	0
T3	224670	8	0	0
T4	5739	0	0	0
T5	1748	0	0	0
T6	30812	0	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	0	0	0
T11	0	9	0	0
T28	0	27	0	0
T29	0	12	0	0
T43	0	44	0	0
T52	0	9	0	0
T78	0	7	0	0
T82	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	14640	0	0
T1	161275	154	0	0
T2	249429	277	0	0
T3	224670	253	0	0
T4	5739	16	0	0
T5	1748	0	0	0
T6	30812	31	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	75	0	0
T11	0	9	0	0
T12	0	35	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	1178	0	0
T1	161275	8	0	0
T2	249429	23	0	0
T3	224670	12	0	0
T4	5739	0	0	0
T5	1748	0	0	0
T6	30812	0	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	0	0	0
T11	0	9	0	0
T28	0	29	0	0
T29	0	13	0	0
T33	0	1	0	0
T43	0	42	0	0
T52	0	13	0	0
T79	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	14640	0	0
T1	161275	154	0	0
T2	249429	277	0	0
T3	224670	253	0	0
T4	5739	16	0	0
T5	1748	0	0	0
T6	30812	31	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	75	0	0
T11	0	9	0	0
T12	0	35	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	1178	0	0
T1	161275	8	0	0
T2	249429	23	0	0
T3	224670	12	0	0
T4	5739	0	0	0
T5	1748	0	0	0
T6	30812	0	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	0	0	0
T11	0	9	0	0
T28	0	29	0	0
T29	0	13	0	0
T33	0	1	0	0
T43	0	42	0	0
T52	0	13	0	0
T79	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	14697	0	0
T1	161275	154	0	0
T2	249429	274	0	0
T3	224670	252	0	0
T4	5739	16	0	0
T5	1748	0	0	0
T6	30812	31	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	75	0	0
T11	0	12	0	0
T12	0	35	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	1240	0	0
T1	161275	7	0	0
T2	249429	20	0	0
T3	224670	10	0	0
T4	5739	0	0	0
T5	1748	0	0	0
T6	30812	0	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	0	0	0
T11	0	12	0	0
T28	0	27	0	0
T29	0	13	0	0
T33	0	1	0	0
T43	0	44	0	0
T52	0	13	0	0
T78	0	9	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	14697	0	0
T1	161275	154	0	0
T2	249429	274	0	0
T3	224670	252	0	0
T4	5739	16	0	0
T5	1748	0	0	0
T6	30812	31	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	75	0	0
T11	0	12	0	0
T12	0	35	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13609035	1240	0	0
T1	161275	7	0	0
T2	249429	20	0	0
T3	224670	10	0	0
T4	5739	0	0	0
T5	1748	0	0	0
T6	30812	0	0	0
T7	5849	0	0	0
T8	1885	0	0	0
T9	5826	0	0	0
T10	29259	0	0	0
T11	0	12	0	0
T28	0	27	0	0
T29	0	13	0	0
T33	0	1	0	0
T43	0	44	0	0
T52	0	13	0	0
T78	0	9	0	0