Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12834908	9710	0	0
alert_regwen_rd_A	12834908	5800	0	0
cpu_regwen_rd_A	12834908	5778	0	0
sw_rst_ctrl_n_0_rd_A	12834908	9053	0	0
sw_rst_ctrl_n_1_rd_A	12834908	8932	0	0
sw_rst_ctrl_n_2_rd_A	12834908	8787	0	0
sw_rst_ctrl_n_3_rd_A	12834908	8657	0	0
sw_rst_ctrl_n_4_rd_A	12834908	8967	0	0
sw_rst_ctrl_n_5_rd_A	12834908	8520	0	0
sw_rst_ctrl_n_6_rd_A	12834908	8638	0	0
sw_rst_ctrl_n_7_rd_A	12834908	9000	0	0
sw_rst_regwen_0_rd_A	12834908	6259	0	0
sw_rst_regwen_1_rd_A	12834908	6081	0	0
sw_rst_regwen_2_rd_A	12834908	5953	0	0
sw_rst_regwen_3_rd_A	12834908	5958	0	0
sw_rst_regwen_4_rd_A	12834908	6065	0	0
sw_rst_regwen_5_rd_A	12834908	6079	0	0
sw_rst_regwen_6_rd_A	12834908	5878	0	0
sw_rst_regwen_7_rd_A	12834908	5993	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	9710	0	0
T54	3852	60	0	0
T55	4780	119	0	0
T56	21225	4	0	0
T57	9851	1	0	0
T58	3000	17	0	0
T59	2905	461	0	0
T61	20196	1	0	0
T83	4127	11	0	0
T84	4044	200	0	0
T85	3093	284	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	5800	0	0
T12	46630	122	0	0
T13	2562	0	0	0
T14	2495	0	0	0
T15	26032	0	0	0
T16	2287	0	0	0
T26	6075	0	0	0
T27	25848	0	0	0
T28	116794	0	0	0
T29	8766	0	0	0
T43	103200	0	0	0
T88	0	66	0	0
T92	0	319	0	0
T95	0	652	0	0
T96	0	60	0	0
T97	0	19	0	0
T119	0	47	0	0
T120	0	198	0	0
T121	0	105	0	0
T122	0	21	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	5778	0	0
T12	46630	95	0	0
T13	2562	0	0	0
T14	2495	0	0	0
T15	26032	0	0	0
T16	2287	0	0	0
T26	6075	0	0	0
T27	25848	0	0	0
T28	116794	0	0	0
T29	8766	0	0	0
T43	103200	0	0	0
T88	0	86	0	0
T92	0	344	0	0
T95	0	635	0	0
T96	0	75	0	0
T97	0	30	0	0
T119	0	12	0	0
T120	0	202	0	0
T121	0	88	0	0
T122	0	24	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	9053	0	0
T4	4575	39	0	0
T5	1729	0	0	0
T6	26083	0	0	0
T7	5684	0	0	0
T8	1795	0	0	0
T9	5089	0	0	0
T10	26249	0	0	0
T11	3262	0	0	0
T12	46630	125	0	0
T13	2562	0	0	0
T26	0	11	0	0
T81	0	15	0	0
T82	0	10	0	0
T88	0	105	0	0
T123	0	65	0	0
T124	0	30	0	0
T125	0	15	0	0
T126	0	78	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	8932	0	0
T4	4575	37	0	0
T5	1729	0	0	0
T6	26083	0	0	0
T7	5684	0	0	0
T8	1795	0	0	0
T9	5089	0	0	0
T10	26249	0	0	0
T11	3262	0	0	0
T12	46630	88	0	0
T13	2562	0	0	0
T26	0	20	0	0
T81	0	7	0	0
T82	0	18	0	0
T88	0	85	0	0
T123	0	65	0	0
T124	0	18	0	0
T125	0	13	0	0
T126	0	83	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	8787	0	0
T4	4575	28	0	0
T5	1729	0	0	0
T6	26083	0	0	0
T7	5684	0	0	0
T8	1795	0	0	0
T9	5089	0	0	0
T10	26249	0	0	0
T11	3262	0	0	0
T12	46630	104	0	0
T13	2562	0	0	0
T26	0	5	0	0
T81	0	10	0	0
T82	0	18	0	0
T88	0	85	0	0
T123	0	79	0	0
T124	0	31	0	0
T125	0	11	0	0
T126	0	55	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	8657	0	0
T4	4575	52	0	0
T5	1729	0	0	0
T6	26083	0	0	0
T7	5684	0	0	0
T8	1795	0	0	0
T9	5089	0	0	0
T10	26249	0	0	0
T11	3262	0	0	0
T12	46630	90	0	0
T13	2562	0	0	0
T26	0	8	0	0
T81	0	8	0	0
T82	0	7	0	0
T88	0	78	0	0
T123	0	44	0	0
T124	0	2	0	0
T125	0	10	0	0
T126	0	96	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	8967	0	0
T4	4575	24	0	0
T5	1729	0	0	0
T6	26083	0	0	0
T7	5684	0	0	0
T8	1795	0	0	0
T9	5089	0	0	0
T10	26249	0	0	0
T11	3262	0	0	0
T12	46630	79	0	0
T13	2562	0	0	0
T26	0	22	0	0
T81	0	21	0	0
T82	0	13	0	0
T88	0	85	0	0
T123	0	57	0	0
T124	0	15	0	0
T125	0	15	0	0
T126	0	76	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	8520	0	0
T4	4575	59	0	0
T5	1729	0	0	0
T6	26083	0	0	0
T7	5684	0	0	0
T8	1795	0	0	0
T9	5089	0	0	0
T10	26249	0	0	0
T11	3262	0	0	0
T12	46630	101	0	0
T13	2562	0	0	0
T26	0	20	0	0
T81	0	3	0	0
T82	0	5	0	0
T88	0	77	0	0
T123	0	49	0	0
T124	0	28	0	0
T125	0	16	0	0
T126	0	77	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	8638	0	0
T4	4575	24	0	0
T5	1729	0	0	0
T6	26083	0	0	0
T7	5684	0	0	0
T8	1795	0	0	0
T9	5089	0	0	0
T10	26249	0	0	0
T11	3262	0	0	0
T12	46630	86	0	0
T13	2562	0	0	0
T26	0	9	0	0
T81	0	9	0	0
T82	0	9	0	0
T88	0	95	0	0
T123	0	56	0	0
T124	0	11	0	0
T125	0	7	0	0
T126	0	82	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	9000	0	0
T4	4575	30	0	0
T5	1729	0	0	0
T6	26083	0	0	0
T7	5684	0	0	0
T8	1795	0	0	0
T9	5089	0	0	0
T10	26249	0	0	0
T11	3262	0	0	0
T12	46630	99	0	0
T13	2562	0	0	0
T26	0	13	0	0
T81	0	15	0	0
T82	0	13	0	0
T88	0	72	0	0
T123	0	59	0	0
T124	0	18	0	0
T125	0	16	0	0
T126	0	90	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	6259	0	0
T12	46630	122	0	0
T13	2562	0	0	0
T14	2495	0	0	0
T15	26032	0	0	0
T16	2287	0	0	0
T26	6075	8	0	0
T27	25848	0	0	0
T28	116794	0	0	0
T29	8766	0	0	0
T43	103200	0	0	0
T81	0	1	0	0
T82	0	5	0	0
T88	0	56	0	0
T97	0	29	0	0
T119	0	25	0	0
T125	0	2	0	0
T126	0	14	0	0
T127	0	30	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	6081	0	0
T12	46630	102	0	0
T13	2562	0	0	0
T14	2495	0	0	0
T15	26032	0	0	0
T16	2287	0	0	0
T26	6075	10	0	0
T27	25848	0	0	0
T28	116794	0	0	0
T29	8766	0	0	0
T43	103200	0	0	0
T81	0	6	0	0
T82	0	7	0	0
T88	0	78	0	0
T97	0	34	0	0
T119	0	30	0	0
T120	0	161	0	0
T126	0	14	0	0
T127	0	46	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	5953	0	0
T12	46630	93	0	0
T13	2562	0	0	0
T14	2495	0	0	0
T15	26032	0	0	0
T16	2287	0	0	0
T26	6075	7	0	0
T27	25848	0	0	0
T28	116794	0	0	0
T29	8766	0	0	0
T43	103200	0	0	0
T81	0	10	0	0
T82	0	10	0	0
T88	0	78	0	0
T97	0	12	0	0
T119	0	28	0	0
T125	0	2	0	0
T126	0	16	0	0
T127	0	34	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	5958	0	0
T12	46630	94	0	0
T13	2562	0	0	0
T14	2495	0	0	0
T15	26032	0	0	0
T16	2287	0	0	0
T26	6075	8	0	0
T27	25848	0	0	0
T28	116794	0	0	0
T29	8766	0	0	0
T43	103200	0	0	0
T82	0	12	0	0
T88	0	87	0	0
T97	0	30	0	0
T119	0	20	0	0
T120	0	175	0	0
T125	0	8	0	0
T126	0	20	0	0
T127	0	26	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	6065	0	0
T12	46630	82	0	0
T13	2562	0	0	0
T14	2495	0	0	0
T15	26032	0	0	0
T16	2287	0	0	0
T26	6075	0	0	0
T27	25848	0	0	0
T28	116794	0	0	0
T29	8766	0	0	0
T43	103200	0	0	0
T81	0	4	0	0
T82	0	10	0	0
T88	0	88	0	0
T97	0	45	0	0
T119	0	31	0	0
T120	0	216	0	0
T125	0	10	0	0
T126	0	7	0	0
T127	0	24	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	6079	0	0
T12	46630	99	0	0
T13	2562	0	0	0
T14	2495	0	0	0
T15	26032	0	0	0
T16	2287	0	0	0
T26	6075	5	0	0
T27	25848	0	0	0
T28	116794	0	0	0
T29	8766	0	0	0
T43	103200	0	0	0
T81	0	12	0	0
T82	0	4	0	0
T88	0	95	0	0
T97	0	8	0	0
T119	0	16	0	0
T125	0	8	0	0
T126	0	9	0	0
T127	0	53	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	5878	0	0
T12	46630	114	0	0
T13	2562	0	0	0
T14	2495	0	0	0
T15	26032	0	0	0
T16	2287	0	0	0
T26	6075	4	0	0
T27	25848	0	0	0
T28	116794	0	0	0
T29	8766	0	0	0
T43	103200	0	0	0
T81	0	10	0	0
T82	0	4	0	0
T88	0	97	0	0
T97	0	25	0	0
T119	0	12	0	0
T125	0	10	0	0
T126	0	33	0	0
T127	0	24	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12834908	5993	0	0
T12	46630	104	0	0
T13	2562	0	0	0
T14	2495	0	0	0
T15	26032	0	0	0
T16	2287	0	0	0
T26	6075	8	0	0
T27	25848	0	0	0
T28	116794	0	0	0
T29	8766	0	0	0
T43	103200	0	0	0
T81	0	4	0	0
T88	0	93	0	0
T97	0	23	0	0
T119	0	40	0	0
T120	0	165	0	0
T125	0	9	0	0
T126	0	16	0	0
T127	0	31	0	0