Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	580311	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

349248

1

T1

132

T3

3096

T5

124

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	494908	1			T1	186		T2	1		T3	4609
values[0x0]	217171	1			T1	105		T3	1985		T5	88
values[0x1]	217480	1			T1	88		T3	2026		T5	88

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	486579	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

442980

1

T1

166

T3

3992

T5

156

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3062	1			T3	45		T6	6		T10	13
valid_sources[0x01]	3394	1			T3	19		T6	12		T10	20
valid_sources[0x02]	3426	1			T3	26		T6	14		T10	15
valid_sources[0x03]	3485	1			T3	51		T6	15		T10	11
valid_sources[0x04]	6755	1			T3	23		T6	6		T10	12
valid_sources[0x05]	2849	1			T3	19		T6	6		T10	7
valid_sources[0x06]	3731	1			T3	45		T6	13		T10	12
valid_sources[0x07]	3120	1			T3	23		T6	9		T10	8
valid_sources[0x08]	3306	1			T1	6		T3	29		T6	4
valid_sources[0x09]	3165	1			T3	28		T6	10		T10	14
valid_sources[0x0a]	2874	1			T3	41		T6	11		T10	6
valid_sources[0x0b]	3601	1			T3	27		T6	11		T10	7
valid_sources[0x0c]	3025	1			T3	40		T6	11		T10	8
valid_sources[0x0d]	3856	1			T1	6		T3	24		T5	60
valid_sources[0x0e]	2977	1			T3	39		T6	4		T10	11
valid_sources[0x0f]	3663	1			T1	2		T3	33		T6	5
valid_sources[0x10]	7078	1			T1	14		T3	34		T6	8
valid_sources[0x11]	3348	1			T3	34		T6	12		T10	7
valid_sources[0x12]	3038	1			T3	33		T6	7		T10	6
valid_sources[0x13]	3259	1			T3	25		T6	9		T10	8
valid_sources[0x14]	4038	1			T3	28		T6	13		T10	13
valid_sources[0x15]	2779	1			T3	47		T6	2		T10	12
valid_sources[0x16]	6237	1			T3	29		T6	16		T9	1
valid_sources[0x17]	2892	1			T3	30		T6	5		T10	14
valid_sources[0x18]	2744	1			T3	29		T6	14		T10	5
valid_sources[0x19]	3159	1			T3	40		T6	16		T10	3
valid_sources[0x1a]	4320	1			T3	32		T6	16		T10	11
valid_sources[0x1b]	3068	1			T3	24		T6	30		T10	13
valid_sources[0x1c]	3564	1			T3	41		T6	7		T10	8
valid_sources[0x1d]	3930	1			T3	28		T6	17		T10	9
valid_sources[0x1e]	3064	1			T3	36		T6	11		T10	7
valid_sources[0x1f]	3327	1			T3	36		T6	14		T10	11
valid_sources[0x20]	3099	1			T3	37		T6	8		T10	6
valid_sources[0x21]	3356	1			T3	41		T6	7		T10	9
valid_sources[0x22]	2840	1			T3	35		T6	7		T10	9
valid_sources[0x23]	3132	1			T1	2		T3	29		T6	9
valid_sources[0x24]	3124	1			T3	20		T6	15		T10	14
valid_sources[0x25]	3629	1			T3	34		T6	4		T10	9
valid_sources[0x26]	2978	1			T1	4		T3	42		T6	15
valid_sources[0x27]	3660	1			T3	38		T6	7		T10	11
valid_sources[0x28]	4452	1			T3	47		T6	9		T10	13
valid_sources[0x29]	6627	1			T3	25		T6	12		T10	13
valid_sources[0x2a]	4171	1			T3	31		T5	32		T6	14
valid_sources[0x2b]	2763	1			T3	26		T6	14		T10	6
valid_sources[0x2c]	3814	1			T3	31		T6	2		T10	13
valid_sources[0x2d]	2997	1			T3	23		T6	8		T10	9
valid_sources[0x2e]	3233	1			T3	35		T6	10		T10	20
valid_sources[0x2f]	3319	1			T3	40		T6	7		T10	10
valid_sources[0x30]	3431	1			T3	45		T6	14		T10	18
valid_sources[0x31]	3310	1			T3	34		T6	11		T10	8
valid_sources[0x32]	3089	1			T1	5		T3	39		T6	10
valid_sources[0x33]	3059	1			T3	42		T6	8		T10	12
valid_sources[0x34]	3393	1			T3	23		T6	16		T10	18
valid_sources[0x35]	3548	1			T3	24		T6	12		T10	18
valid_sources[0x36]	4264	1			T3	45		T6	7		T10	8
valid_sources[0x37]	3271	1			T3	42		T6	9		T10	9
valid_sources[0x38]	3351	1			T1	1		T3	33		T6	2
valid_sources[0x39]	3218	1			T3	31		T6	2		T10	9
valid_sources[0x3a]	3817	1			T3	33		T6	6		T10	2
valid_sources[0x3b]	4004	1			T3	31		T6	11		T10	9
valid_sources[0x3c]	3152	1			T3	25		T6	14		T10	12
valid_sources[0x3d]	2667	1			T3	33		T6	10		T10	9
valid_sources[0x3e]	2709	1			T3	35		T6	16		T10	10
valid_sources[0x3f]	3225	1			T3	40		T6	19		T10	8
valid_sources[0x40]	3179	1			T3	27		T6	14		T10	9
valid_sources[0x41]	3244	1			T3	40		T6	25		T10	13
valid_sources[0x42]	2924	1			T3	35		T6	19		T10	6
valid_sources[0x43]	2784	1			T3	38		T6	11		T10	10
valid_sources[0x44]	6412	1			T3	36		T6	12		T10	7
valid_sources[0x45]	6647	1			T1	2		T3	38		T6	11
valid_sources[0x46]	3583	1			T3	29		T6	28		T10	8
valid_sources[0x47]	4406	1			T3	44		T6	7		T10	10
valid_sources[0x48]	3281	1			T3	36		T6	16		T10	4
valid_sources[0x49]	5553	1			T3	51		T6	10		T10	4
valid_sources[0x4a]	3541	1			T3	32		T6	16		T10	12
valid_sources[0x4b]	4009	1			T3	36		T6	7		T10	13
valid_sources[0x4c]	3417	1			T3	28		T6	10		T10	14
valid_sources[0x4d]	4062	1			T1	10		T3	23		T6	6
valid_sources[0x4e]	4555	1			T3	30		T6	12		T10	16
valid_sources[0x4f]	3375	1			T3	35		T6	10		T10	7
valid_sources[0x50]	4022	1			T3	48		T6	17		T10	15
valid_sources[0x51]	3190	1			T1	18		T3	28		T6	1
valid_sources[0x52]	3206	1			T3	48		T6	12		T10	14
valid_sources[0x53]	3926	1			T3	38		T6	19		T10	10
valid_sources[0x54]	3167	1			T1	2		T3	38		T6	9
valid_sources[0x55]	4097	1			T3	42		T6	14		T10	7
valid_sources[0x56]	2927	1			T3	37		T6	7		T10	9
valid_sources[0x57]	3670	1			T1	1		T3	35		T6	13
valid_sources[0x58]	2737	1			T3	30		T6	6		T10	20
valid_sources[0x59]	3660	1			T3	40		T6	14		T10	11
valid_sources[0x5a]	2952	1			T3	26		T6	11		T10	6
valid_sources[0x5b]	2847	1			T3	23		T6	14		T10	8
valid_sources[0x5c]	3567	1			T3	34		T6	10		T10	9
valid_sources[0x5d]	3335	1			T3	30		T6	23		T10	16
valid_sources[0x5e]	4757	1			T3	41		T6	4		T10	11
valid_sources[0x5f]	3408	1			T3	43		T6	7		T10	18
valid_sources[0x60]	4272	1			T3	35		T6	9		T10	11
valid_sources[0x61]	3220	1			T3	39		T6	11		T10	7
valid_sources[0x62]	3361	1			T3	27		T6	9		T10	6
valid_sources[0x63]	2934	1			T1	8		T3	31		T6	12
valid_sources[0x64]	3482	1			T3	33		T5	8		T6	16
valid_sources[0x65]	2973	1			T3	39		T4	1		T6	7
valid_sources[0x66]	3249	1			T1	10		T3	29		T6	3
valid_sources[0x67]	3008	1			T3	41		T6	29		T10	7
valid_sources[0x68]	3193	1			T3	37		T6	18		T10	16
valid_sources[0x69]	3104	1			T3	33		T6	3		T13	35
valid_sources[0x6a]	3895	1			T3	34		T6	15		T13	6
valid_sources[0x6b]	4298	1			T1	18		T3	32		T6	18
valid_sources[0x6c]	3195	1			T1	2		T3	25		T6	5
valid_sources[0x6d]	6068	1			T3	30		T6	9		T10	16
valid_sources[0x6e]	3573	1			T1	1		T3	34		T6	5
valid_sources[0x6f]	3235	1			T3	45		T6	13		T10	13
valid_sources[0x70]	3527	1			T3	30		T6	5		T10	12
valid_sources[0x71]	3371	1			T3	39		T6	6		T10	15
valid_sources[0x72]	3240	1			T3	36		T6	7		T10	10
valid_sources[0x73]	2953	1			T3	46		T6	11		T10	2
valid_sources[0x74]	3240	1			T3	31		T6	12		T10	8
valid_sources[0x75]	3351	1			T3	47		T6	3		T10	21
valid_sources[0x76]	3242	1			T3	23		T6	8		T10	12
valid_sources[0x77]	3220	1			T3	33		T6	2		T10	11
valid_sources[0x78]	6437	1			T1	4		T3	37		T6	5
valid_sources[0x79]	3462	1			T1	7		T3	24		T6	7
valid_sources[0x7a]	3534	1			T1	8		T3	32		T6	7
valid_sources[0x7b]	3317	1			T3	32		T5	2		T6	12
valid_sources[0x7c]	3633	1			T1	6		T3	33		T6	12
valid_sources[0x7d]	3039	1			T3	26		T6	18		T10	20
valid_sources[0x7e]	4067	1			T1	7		T3	28		T6	7
valid_sources[0x7f]	3374	1			T3	43		T6	2		T10	11
valid_sources[0x80]	3162	1			T1	4		T3	32		T6	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

232405

1

T1

89

T3

2114

T5

86

values[0x0]

all_enables

biggest_size

76137

1

T1

32

T3

677

T5

22

values[0x1]

all_enables

biggest_size

40706

1

T1

11

T3

305

T5

16