Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T3,T6,T10

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	50880147	8509	0	0
CascadeEffAonToRstPorAboveRise_A	50880147	8509	0	0
CascadeEffAonToRstPorIoAboveFall_A	48843190	8509	0	0
CascadeEffAonToRstPorIoAboveRise_A	48843190	8509	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24422450	8509	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24422450	8509	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12210794	8509	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12210794	8509	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24422406	8509	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24422406	8509	0	0
CascadeLcToLcAboveFall_A	50880147	20871	0	0
CascadeLcToLcAboveRise_A	50880147	20871	0	0
CascadeLcToLcAonAboveFall_A	1541702	20871	0	0
CascadeLcToLcAonAboveRise_A	1541702	20871	0	0
CascadeLcToLcShadowedAboveFall_A	50880147	20871	0	0
CascadeLcToLcShadowedAboveRise_A	50880147	20871	0	0
CascadePorToAonAboveFall_A	1541702	6862	0	0
CascadeSysToSysAboveFall_A	50880147	20871	0	0
CascadeSysToSysAboveRise_A	50880147	20871	0	0
ScanRstToAonRise_A	1541702	196	0	0
StablePorToAonRise_A	1541702	8509	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10827177	20871	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10827177	20871	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10827177	20871	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10827177	20871	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12210794	20871	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12210794	20871	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10827177	20871	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10827177	20871	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10827177	20871	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10827177	20871	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50880147	8509	0	0
T1	11709	2	0	0
T2	12160	2	0	0
T3	548250	56	0	0
T4	16618	2	0	0
T5	24761	1	0	0
T6	144118	22	0	0
T7	24983	8	0	0
T8	24689	8	0	0
T9	22129	2	0	0
T10	179135	21	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50880147	8509	0	0
T1	11709	2	0	0
T2	12160	2	0	0
T3	548250	56	0	0
T4	16618	2	0	0
T5	24761	1	0	0
T6	144118	22	0	0
T7	24983	8	0	0
T8	24689	8	0	0
T9	22129	2	0	0
T10	179135	21	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48843190	8509	0	0
T1	11234	2	0	0
T2	11674	2	0	0
T3	526290	56	0	0
T4	15954	2	0	0
T5	23769	1	0	0
T6	138333	22	0	0
T7	23981	8	0	0
T8	23717	8	0	0
T9	21243	2	0	0
T10	171956	21	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48843190	8509	0	0
T1	11234	2	0	0
T2	11674	2	0	0
T3	526290	56	0	0
T4	15954	2	0	0
T5	23769	1	0	0
T6	138333	22	0	0
T7	23981	8	0	0
T8	23717	8	0	0
T9	21243	2	0	0
T10	171956	21	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422450	8509	0	0
T1	5618	2	0	0
T2	5837	2	0	0
T3	263142	56	0	0
T4	7977	2	0	0
T5	11884	1	0	0
T6	69174	22	0	0
T7	11994	8	0	0
T8	11855	8	0	0
T9	10621	2	0	0
T10	85983	21	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422450	8509	0	0
T1	5618	2	0	0
T2	5837	2	0	0
T3	263142	56	0	0
T4	7977	2	0	0
T5	11884	1	0	0
T6	69174	22	0	0
T7	11994	8	0	0
T8	11855	8	0	0
T9	10621	2	0	0
T10	85983	21	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	8509	0	0
T1	2808	2	0	0
T2	2917	2	0	0
T3	131572	56	0	0
T4	3987	2	0	0
T5	5941	1	0	0
T6	34588	22	0	0
T7	5993	8	0	0
T8	5925	8	0	0
T9	5310	2	0	0
T10	42991	21	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	8509	0	0
T1	2808	2	0	0
T2	2917	2	0	0
T3	131572	56	0	0
T4	3987	2	0	0
T5	5941	1	0	0
T6	34588	22	0	0
T7	5993	8	0	0
T8	5925	8	0	0
T9	5310	2	0	0
T10	42991	21	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422406	8509	0	0
T1	5618	2	0	0
T2	5836	2	0	0
T3	263138	56	0	0
T4	7976	2	0	0
T5	11884	1	0	0
T6	69183	22	0	0
T7	11998	8	0	0
T8	11849	8	0	0
T9	10621	2	0	0
T10	85985	21	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422406	8509	0	0
T1	5618	2	0	0
T2	5836	2	0	0
T3	263138	56	0	0
T4	7976	2	0	0
T5	11884	1	0	0
T6	69183	22	0	0
T7	11998	8	0	0
T8	11849	8	0	0
T9	10621	2	0	0
T10	85985	21	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50880147	20871	0	0
T1	11709	6	0	0
T2	12160	2	0	0
T3	548250	152	0	0
T4	16618	2	0	0
T5	24761	20	0	0
T6	144118	50	0	0
T7	24983	8	0	0
T8	24689	8	0	0
T9	22129	2	0	0
T10	179135	51	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50880147	20871	0	0
T1	11709	6	0	0
T2	12160	2	0	0
T3	548250	152	0	0
T4	16618	2	0	0
T5	24761	20	0	0
T6	144118	50	0	0
T7	24983	8	0	0
T8	24689	8	0	0
T9	22129	2	0	0
T10	179135	51	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541702	20871	0	0
T1	350	6	0	0
T2	363	2	0	0
T3	16581	152	0	0
T4	498	2	0	0
T5	742	20	0	0
T6	4367	50	0	0
T7	751	8	0	0
T8	743	8	0	0
T9	662	2	0	0
T10	5411	51	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541702	20871	0	0
T1	350	6	0	0
T2	363	2	0	0
T3	16581	152	0	0
T4	498	2	0	0
T5	742	20	0	0
T6	4367	50	0	0
T7	751	8	0	0
T8	743	8	0	0
T9	662	2	0	0
T10	5411	51	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50880147	20871	0	0
T1	11709	6	0	0
T2	12160	2	0	0
T3	548250	152	0	0
T4	16618	2	0	0
T5	24761	20	0	0
T6	144118	50	0	0
T7	24983	8	0	0
T8	24689	8	0	0
T9	22129	2	0	0
T10	179135	51	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50880147	20871	0	0
T1	11709	6	0	0
T2	12160	2	0	0
T3	548250	152	0	0
T4	16618	2	0	0
T5	24761	20	0	0
T6	144118	50	0	0
T7	24983	8	0	0
T8	24689	8	0	0
T9	22129	2	0	0
T10	179135	51	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541702	6862	0	0
T1	350	1	0	0
T2	363	7	0	0
T3	16581	32	0	0
T4	498	15	0	0
T5	742	1	0	0
T6	4367	12	0	0
T7	751	8	0	0
T8	743	8	0	0
T9	662	21	0	0
T10	5411	11	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50880147	20871	0	0
T1	11709	6	0	0
T2	12160	2	0	0
T3	548250	152	0	0
T4	16618	2	0	0
T5	24761	20	0	0
T6	144118	50	0	0
T7	24983	8	0	0
T8	24689	8	0	0
T9	22129	2	0	0
T10	179135	51	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50880147	20871	0	0
T1	11709	6	0	0
T2	12160	2	0	0
T3	548250	152	0	0
T4	16618	2	0	0
T5	24761	20	0	0
T6	144118	50	0	0
T7	24983	8	0	0
T8	24689	8	0	0
T9	22129	2	0	0
T10	179135	51	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541702	196	0	0
T6	4367	1	0	0
T7	751	0	0	0
T8	743	0	0	0
T9	662	0	0	0
T10	5411	0	0	0
T11	351	0	0	0
T12	485	0	0	0
T13	12914	4	0	0
T14	616	0	0	0
T20	524	0	0	0
T23	0	3	0	0
T86	0	2	0	0
T89	0	7	0	0
T90	0	8	0	0
T91	0	6	0	0
T92	0	6	0	0
T96	0	2	0	0
T97	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541702	8509	0	0
T1	350	2	0	0
T2	363	2	0	0
T3	16581	56	0	0
T4	498	2	0	0
T5	742	1	0	0
T6	4367	22	0	0
T7	751	8	0	0
T8	743	8	0	0
T9	662	2	0	0
T10	5411	21	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10827177	20871	0	0
T1	2519	6	0	0
T2	2803	2	0	0
T3	120815	152	0	0
T4	3849	2	0	0
T5	4561	20	0	0
T6	30133	50	0	0
T7	5258	8	0	0
T8	5766	8	0	0
T9	5219	2	0	0
T10	38544	51	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10827177	20871	0	0
T1	2519	6	0	0
T2	2803	2	0	0
T3	120815	152	0	0
T4	3849	2	0	0
T5	4561	20	0	0
T6	30133	50	0	0
T7	5258	8	0	0
T8	5766	8	0	0
T9	5219	2	0	0
T10	38544	51	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10827177	20871	0	0
T1	2519	6	0	0
T2	2803	2	0	0
T3	120815	152	0	0
T4	3849	2	0	0
T5	4561	20	0	0
T6	30133	50	0	0
T7	5258	8	0	0
T8	5766	8	0	0
T9	5219	2	0	0
T10	38544	51	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10827177	20871	0	0
T1	2519	6	0	0
T2	2803	2	0	0
T3	120815	152	0	0
T4	3849	2	0	0
T5	4561	20	0	0
T6	30133	50	0	0
T7	5258	8	0	0
T8	5766	8	0	0
T9	5219	2	0	0
T10	38544	51	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	20871	0	0
T1	2808	6	0	0
T2	2917	2	0	0
T3	131572	152	0	0
T4	3987	2	0	0
T5	5941	20	0	0
T6	34588	50	0	0
T7	5993	8	0	0
T8	5925	8	0	0
T9	5310	2	0	0
T10	42991	51	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	20871	0	0
T1	2808	6	0	0
T2	2917	2	0	0
T3	131572	152	0	0
T4	3987	2	0	0
T5	5941	20	0	0
T6	34588	50	0	0
T7	5993	8	0	0
T8	5925	8	0	0
T9	5310	2	0	0
T10	42991	51	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10827177	20871	0	0
T1	2519	6	0	0
T2	2803	2	0	0
T3	120815	152	0	0
T4	3849	2	0	0
T5	4561	20	0	0
T6	30133	50	0	0
T7	5258	8	0	0
T8	5766	8	0	0
T9	5219	2	0	0
T10	38544	51	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10827177	20871	0	0
T1	2519	6	0	0
T2	2803	2	0	0
T3	120815	152	0	0
T4	3849	2	0	0
T5	4561	20	0	0
T6	30133	50	0	0
T7	5258	8	0	0
T8	5766	8	0	0
T9	5219	2	0	0
T10	38544	51	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10827177	20871	0	0
T1	2519	6	0	0
T2	2803	2	0	0
T3	120815	152	0	0
T4	3849	2	0	0
T5	4561	20	0	0
T6	30133	50	0	0
T7	5258	8	0	0
T8	5766	8	0	0
T9	5219	2	0	0
T10	38544	51	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10827177	20871	0	0
T1	2519	6	0	0
T2	2803	2	0	0
T3	120815	152	0	0
T4	3849	2	0	0
T5	4561	20	0	0
T6	30133	50	0	0
T7	5258	8	0	0
T8	5766	8	0	0
T9	5219	2	0	0
T10	38544	51	0	0