Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12210794	13255	0	0
gen_assertions[0].RstEnOn_A	12210794	1069	0	0
gen_assertions[0].RstNOff_A	12210794	13255	0	0
gen_assertions[0].RstNOn_A	12210794	1069	0	0
gen_assertions[1].RstEnOff_A	48843190	12067	0	0
gen_assertions[1].RstEnOn_A	48843190	976	0	0
gen_assertions[1].RstNOff_A	48843190	12067	0	0
gen_assertions[1].RstNOn_A	48843190	976	0	0
gen_assertions[2].RstEnOff_A	24422450	12131	0	0
gen_assertions[2].RstEnOn_A	24422450	1006	0	0
gen_assertions[2].RstNOff_A	24422450	12131	0	0
gen_assertions[2].RstNOn_A	24422450	1006	0	0
gen_assertions[3].RstEnOff_A	24422406	12166	0	0
gen_assertions[3].RstEnOn_A	24422406	1027	0	0
gen_assertions[3].RstNOff_A	24422406	12166	0	0
gen_assertions[3].RstNOn_A	24422406	1027	0	0
gen_assertions[4].RstEnOff_A	1541702	20605	0	0
gen_assertions[4].RstEnOn_A	1541702	1089	0	0
gen_assertions[4].RstNOff_A	1541702	20605	0	0
gen_assertions[4].RstNOn_A	1541702	1089	0	0
gen_assertions[5].RstEnOff_A	12210794	13452	0	0
gen_assertions[5].RstEnOn_A	12210794	1119	0	0
gen_assertions[5].RstNOff_A	12210794	13452	0	0
gen_assertions[5].RstNOn_A	12210794	1119	0	0
gen_assertions[6].RstEnOff_A	12210794	13534	0	0
gen_assertions[6].RstEnOn_A	12210794	1209	0	0
gen_assertions[6].RstNOff_A	12210794	13534	0	0
gen_assertions[6].RstNOn_A	12210794	1209	0	0
gen_assertions[7].RstEnOff_A	12210794	13557	0	0
gen_assertions[7].RstEnOn_A	12210794	1228	0	0
gen_assertions[7].RstNOff_A	12210794	13557	0	0
gen_assertions[7].RstNOn_A	12210794	1228	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	13255	0	0
T1	2808	5	0	0
T2	2917	0	0	0
T3	131572	121	0	0
T4	3987	0	0	0
T5	5941	19	0	0
T6	34588	28	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	30	0	0
T11	0	2	0	0
T13	0	185	0	0
T20	0	4	0	0
T21	0	75	0	0
T61	0	7	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	1069	0	0
T1	2808	1	0	0
T2	2917	0	0	0
T3	131572	29	0	0
T4	3987	0	0	0
T5	5941	2	0	0
T6	34588	0	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	0	0	0
T11	0	2	0	0
T13	0	28	0	0
T22	0	1	0	0
T23	0	18	0	0
T37	0	2	0	0
T48	0	4	0	0
T61	0	7	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	13255	0	0
T1	2808	5	0	0
T2	2917	0	0	0
T3	131572	121	0	0
T4	3987	0	0	0
T5	5941	19	0	0
T6	34588	28	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	30	0	0
T11	0	2	0	0
T13	0	185	0	0
T20	0	4	0	0
T21	0	75	0	0
T61	0	7	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	1069	0	0
T1	2808	1	0	0
T2	2917	0	0	0
T3	131572	29	0	0
T4	3987	0	0	0
T5	5941	2	0	0
T6	34588	0	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	0	0	0
T11	0	2	0	0
T13	0	28	0	0
T22	0	1	0	0
T23	0	18	0	0
T37	0	2	0	0
T48	0	4	0	0
T61	0	7	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48843190	12067	0	0
T1	11234	4	0	0
T2	11674	0	0	0
T3	526290	113	0	0
T4	15954	0	0	0
T5	23769	17	0	0
T6	138333	25	0	0
T7	23981	0	0	0
T8	23717	0	0	0
T9	21243	0	0	0
T10	171956	29	0	0
T11	0	4	0	0
T13	0	170	0	0
T20	0	4	0	0
T21	0	70	0	0
T61	0	6	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48843190	976	0	0
T3	526290	30	0	0
T4	15954	0	0	0
T5	23769	0	0	0
T6	138333	0	0	0
T7	23981	0	0	0
T8	23717	0	0	0
T9	21243	0	0	0
T10	171956	0	0	0
T11	11244	4	0	0
T12	15572	0	0	0
T13	0	24	0	0
T23	0	16	0	0
T48	0	6	0	0
T55	0	9	0	0
T61	0	6	0	0
T75	0	11	0	0
T76	0	10	0	0
T77	0	2	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48843190	12067	0	0
T1	11234	4	0	0
T2	11674	0	0	0
T3	526290	113	0	0
T4	15954	0	0	0
T5	23769	17	0	0
T6	138333	25	0	0
T7	23981	0	0	0
T8	23717	0	0	0
T9	21243	0	0	0
T10	171956	29	0	0
T11	0	4	0	0
T13	0	170	0	0
T20	0	4	0	0
T21	0	70	0	0
T61	0	6	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48843190	976	0	0
T3	526290	30	0	0
T4	15954	0	0	0
T5	23769	0	0	0
T6	138333	0	0	0
T7	23981	0	0	0
T8	23717	0	0	0
T9	21243	0	0	0
T10	171956	0	0	0
T11	11244	4	0	0
T12	15572	0	0	0
T13	0	24	0	0
T23	0	16	0	0
T48	0	6	0	0
T55	0	9	0	0
T61	0	6	0	0
T75	0	11	0	0
T76	0	10	0	0
T77	0	2	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422450	12131	0	0
T1	5618	4	0	0
T2	5837	0	0	0
T3	263142	112	0	0
T4	7977	0	0	0
T5	11884	17	0	0
T6	69174	25	0	0
T7	11994	0	0	0
T8	11855	0	0	0
T9	10621	0	0	0
T10	85983	29	0	0
T11	0	4	0	0
T13	0	173	0	0
T20	0	4	0	0
T21	0	70	0	0
T61	0	6	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422450	1006	0	0
T3	263142	29	0	0
T4	7977	0	0	0
T5	11884	0	0	0
T6	69174	0	0	0
T7	11994	0	0	0
T8	11855	0	0	0
T9	10621	0	0	0
T10	85983	0	0	0
T11	5621	4	0	0
T12	7786	0	0	0
T13	0	27	0	0
T23	0	14	0	0
T48	0	7	0	0
T49	0	1	0	0
T55	0	11	0	0
T59	0	1	0	0
T61	0	6	0	0
T75	0	7	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422450	12131	0	0
T1	5618	4	0	0
T2	5837	0	0	0
T3	263142	112	0	0
T4	7977	0	0	0
T5	11884	17	0	0
T6	69174	25	0	0
T7	11994	0	0	0
T8	11855	0	0	0
T9	10621	0	0	0
T10	85983	29	0	0
T11	0	4	0	0
T13	0	173	0	0
T20	0	4	0	0
T21	0	70	0	0
T61	0	6	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422450	1006	0	0
T3	263142	29	0	0
T4	7977	0	0	0
T5	11884	0	0	0
T6	69174	0	0	0
T7	11994	0	0	0
T8	11855	0	0	0
T9	10621	0	0	0
T10	85983	0	0	0
T11	5621	4	0	0
T12	7786	0	0	0
T13	0	27	0	0
T23	0	14	0	0
T48	0	7	0	0
T49	0	1	0	0
T55	0	11	0	0
T59	0	1	0	0
T61	0	6	0	0
T75	0	7	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422406	12166	0	0
T1	5618	4	0	0
T2	5836	0	0	0
T3	263138	114	0	0
T4	7976	0	0	0
T5	11884	17	0	0
T6	69183	25	0	0
T7	11998	0	0	0
T8	11849	0	0	0
T9	10621	0	0	0
T10	85985	29	0	0
T11	0	5	0	0
T13	0	173	0	0
T20	0	4	0	0
T21	0	70	0	0
T61	0	8	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422406	1027	0	0
T3	263138	31	0	0
T4	7976	0	0	0
T5	11884	0	0	0
T6	69183	0	0	0
T7	11998	0	0	0
T8	11849	0	0	0
T9	10621	0	0	0
T10	85985	0	0	0
T11	5621	5	0	0
T12	7786	0	0	0
T13	0	27	0	0
T23	0	13	0	0
T48	0	7	0	0
T49	0	1	0	0
T55	0	11	0	0
T61	0	8	0	0
T75	0	10	0	0
T76	0	11	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422406	12166	0	0
T1	5618	4	0	0
T2	5836	0	0	0
T3	263138	114	0	0
T4	7976	0	0	0
T5	11884	17	0	0
T6	69183	25	0	0
T7	11998	0	0	0
T8	11849	0	0	0
T9	10621	0	0	0
T10	85985	29	0	0
T11	0	5	0	0
T13	0	173	0	0
T20	0	4	0	0
T21	0	70	0	0
T61	0	8	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24422406	1027	0	0
T3	263138	31	0	0
T4	7976	0	0	0
T5	11884	0	0	0
T6	69183	0	0	0
T7	11998	0	0	0
T8	11849	0	0	0
T9	10621	0	0	0
T10	85985	0	0	0
T11	5621	5	0	0
T12	7786	0	0	0
T13	0	27	0	0
T23	0	13	0	0
T48	0	7	0	0
T49	0	1	0	0
T55	0	11	0	0
T61	0	8	0	0
T75	0	10	0	0
T76	0	11	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541702	20605	0	0
T1	350	6	0	0
T2	363	2	0	0
T3	16581	173	0	0
T4	498	2	0	0
T5	742	20	0	0
T6	4367	50	0	0
T7	751	3	0	0
T8	743	3	0	0
T9	662	2	0	0
T10	5411	50	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541702	1089	0	0
T3	16581	23	0	0
T4	498	0	0	0
T5	742	0	0	0
T6	4367	0	0	0
T7	751	0	0	0
T8	743	0	0	0
T9	662	0	0	0
T10	5411	0	0	0
T11	351	6	0	0
T12	485	0	0	0
T13	0	26	0	0
T23	0	17	0	0
T48	0	8	0	0
T55	0	8	0	0
T61	0	11	0	0
T75	0	11	0	0
T76	0	12	0	0
T77	0	5	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541702	20605	0	0
T1	350	6	0	0
T2	363	2	0	0
T3	16581	173	0	0
T4	498	2	0	0
T5	742	20	0	0
T6	4367	50	0	0
T7	751	3	0	0
T8	743	3	0	0
T9	662	2	0	0
T10	5411	50	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541702	1089	0	0
T3	16581	23	0	0
T4	498	0	0	0
T5	742	0	0	0
T6	4367	0	0	0
T7	751	0	0	0
T8	743	0	0	0
T9	662	0	0	0
T10	5411	0	0	0
T11	351	6	0	0
T12	485	0	0	0
T13	0	26	0	0
T23	0	17	0	0
T48	0	8	0	0
T55	0	8	0	0
T61	0	11	0	0
T75	0	11	0	0
T76	0	12	0	0
T77	0	5	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	13452	0	0
T1	2808	4	0	0
T2	2917	0	0	0
T3	131572	125	0	0
T4	3987	0	0	0
T5	5941	19	0	0
T6	34588	28	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	30	0	0
T11	0	8	0	0
T13	0	177	0	0
T20	0	4	0	0
T21	0	75	0	0
T61	0	10	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	1119	0	0
T3	131572	31	0	0
T4	3987	0	0	0
T5	5941	0	0	0
T6	34588	0	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	0	0	0
T11	2810	8	0	0
T12	3892	0	0	0
T13	0	20	0	0
T23	0	14	0	0
T48	0	10	0	0
T55	0	12	0	0
T61	0	10	0	0
T75	0	12	0	0
T76	0	12	0	0
T77	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	13452	0	0
T1	2808	4	0	0
T2	2917	0	0	0
T3	131572	125	0	0
T4	3987	0	0	0
T5	5941	19	0	0
T6	34588	28	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	30	0	0
T11	0	8	0	0
T13	0	177	0	0
T20	0	4	0	0
T21	0	75	0	0
T61	0	10	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	1119	0	0
T3	131572	31	0	0
T4	3987	0	0	0
T5	5941	0	0	0
T6	34588	0	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	0	0	0
T11	2810	8	0	0
T12	3892	0	0	0
T13	0	20	0	0
T23	0	14	0	0
T48	0	10	0	0
T55	0	12	0	0
T61	0	10	0	0
T75	0	12	0	0
T76	0	12	0	0
T77	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	13534	0	0
T1	2808	4	0	0
T2	2917	0	0	0
T3	131572	124	0	0
T4	3987	0	0	0
T5	5941	19	0	0
T6	34588	28	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	30	0	0
T11	0	7	0	0
T13	0	185	0	0
T20	0	4	0	0
T21	0	75	0	0
T61	0	11	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	1209	0	0
T3	131572	31	0	0
T4	3987	0	0	0
T5	5941	0	0	0
T6	34588	0	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	0	0	0
T11	2810	7	0	0
T12	3892	0	0	0
T13	0	28	0	0
T23	0	16	0	0
T48	0	11	0	0
T55	0	14	0	0
T61	0	11	0	0
T75	0	11	0	0
T76	0	13	0	0
T77	0	7	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	13534	0	0
T1	2808	4	0	0
T2	2917	0	0	0
T3	131572	124	0	0
T4	3987	0	0	0
T5	5941	19	0	0
T6	34588	28	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	30	0	0
T11	0	7	0	0
T13	0	185	0	0
T20	0	4	0	0
T21	0	75	0	0
T61	0	11	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	1209	0	0
T3	131572	31	0	0
T4	3987	0	0	0
T5	5941	0	0	0
T6	34588	0	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	0	0	0
T11	2810	7	0	0
T12	3892	0	0	0
T13	0	28	0	0
T23	0	16	0	0
T48	0	11	0	0
T55	0	14	0	0
T61	0	11	0	0
T75	0	11	0	0
T76	0	13	0	0
T77	0	7	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	13557	0	0
T1	2808	5	0	0
T2	2917	0	0	0
T3	131572	124	0	0
T4	3987	0	0	0
T5	5941	19	0	0
T6	34588	28	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	30	0	0
T11	0	9	0	0
T13	0	181	0	0
T20	0	4	0	0
T21	0	75	0	0
T61	0	11	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	1228	0	0
T1	2808	1	0	0
T2	2917	0	0	0
T3	131572	30	0	0
T4	3987	0	0	0
T5	5941	0	0	0
T6	34588	0	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	0	0	0
T11	0	9	0	0
T13	0	24	0	0
T23	0	13	0	0
T48	0	10	0	0
T55	0	15	0	0
T61	0	11	0	0
T75	0	14	0	0
T76	0	14	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	13557	0	0
T1	2808	5	0	0
T2	2917	0	0	0
T3	131572	124	0	0
T4	3987	0	0	0
T5	5941	19	0	0
T6	34588	28	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	30	0	0
T11	0	9	0	0
T13	0	181	0	0
T20	0	4	0	0
T21	0	75	0	0
T61	0	11	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12210794	1228	0	0
T1	2808	1	0	0
T2	2917	0	0	0
T3	131572	30	0	0
T4	3987	0	0	0
T5	5941	0	0	0
T6	34588	0	0	0
T7	5993	0	0	0
T8	5925	0	0	0
T9	5310	0	0	0
T10	42991	0	0	0
T11	0	9	0	0
T13	0	24	0	0
T23	0	13	0	0
T48	0	10	0	0
T55	0	15	0	0
T61	0	11	0	0
T75	0	14	0	0
T76	0	14	0	0