Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11615183	8018	0	0
alert_regwen_rd_A	11615183	4098	0	0
cpu_regwen_rd_A	11615183	4246	0	0
sw_rst_ctrl_n_0_rd_A	11615183	9137	0	0
sw_rst_ctrl_n_1_rd_A	11615183	9038	0	0
sw_rst_ctrl_n_2_rd_A	11615183	9064	0	0
sw_rst_ctrl_n_3_rd_A	11615183	8709	0	0
sw_rst_ctrl_n_4_rd_A	11615183	9047	0	0
sw_rst_ctrl_n_5_rd_A	11615183	9078	0	0
sw_rst_ctrl_n_6_rd_A	11615183	9180	0	0
sw_rst_ctrl_n_7_rd_A	11615183	9223	0	0
sw_rst_regwen_0_rd_A	11615183	4480	0	0
sw_rst_regwen_1_rd_A	11615183	4616	0	0
sw_rst_regwen_2_rd_A	11615183	4468	0	0
sw_rst_regwen_3_rd_A	11615183	4656	0	0
sw_rst_regwen_4_rd_A	11615183	4447	0	0
sw_rst_regwen_5_rd_A	11615183	4546	0	0
sw_rst_regwen_6_rd_A	11615183	4510	0	0
sw_rst_regwen_7_rd_A	11615183	4303	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	8018	0	0
T62	20589	2	0	0
T65	10160	1	0	0
T66	2612	124	0	0
T67	7899	189	0	0
T68	2838	115	0	0
T69	4245	265	0	0
T78	2340	8	0	0
T79	20410	2	0	0
T80	2288	25	0	0
T84	9687	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	4098	0	0
T3	120815	69	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	76	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	311	0	0
T86	0	75	0	0
T93	0	77	0	0
T94	0	106	0	0
T95	0	42	0	0
T115	0	36	0	0
T116	0	191	0	0
T117	0	48	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	4246	0	0
T3	120815	64	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	73	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	341	0	0
T86	0	71	0	0
T93	0	75	0	0
T94	0	102	0	0
T95	0	39	0	0
T115	0	78	0	0
T116	0	154	0	0
T117	0	40	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	9137	0	0
T3	120815	274	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	70	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	530	0	0
T48	0	192	0	0
T49	0	5	0	0
T86	0	54	0	0
T118	0	12	0	0
T119	0	17	0	0
T120	0	35	0	0
T121	0	56	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	9038	0	0
T3	120815	267	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	62	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	577	0	0
T48	0	177	0	0
T49	0	19	0	0
T86	0	71	0	0
T118	0	8	0	0
T119	0	7	0	0
T120	0	23	0	0
T121	0	53	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	9064	0	0
T3	120815	287	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	72	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	547	0	0
T48	0	143	0	0
T86	0	79	0	0
T118	0	17	0	0
T119	0	5	0	0
T120	0	19	0	0
T121	0	47	0	0
T122	0	69	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	8709	0	0
T3	120815	284	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	81	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	526	0	0
T48	0	138	0	0
T49	0	2	0	0
T86	0	57	0	0
T118	0	12	0	0
T119	0	12	0	0
T120	0	34	0	0
T121	0	58	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	9047	0	0
T3	120815	306	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	67	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	598	0	0
T48	0	164	0	0
T49	0	7	0	0
T86	0	57	0	0
T118	0	10	0	0
T119	0	7	0	0
T120	0	36	0	0
T121	0	51	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	9078	0	0
T3	120815	324	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	52	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	528	0	0
T48	0	166	0	0
T49	0	2	0	0
T86	0	71	0	0
T118	0	26	0	0
T119	0	10	0	0
T120	0	34	0	0
T121	0	62	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	9180	0	0
T3	120815	331	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	80	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	501	0	0
T48	0	169	0	0
T49	0	2	0	0
T86	0	81	0	0
T118	0	6	0	0
T119	0	6	0	0
T120	0	27	0	0
T121	0	76	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	9223	0	0
T3	120815	299	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	69	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	573	0	0
T48	0	146	0	0
T86	0	61	0	0
T118	0	6	0	0
T119	0	2	0	0
T120	0	35	0	0
T121	0	59	0	0
T122	0	56	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	4480	0	0
T3	120815	52	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	80	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	315	0	0
T48	0	33	0	0
T49	0	3	0	0
T86	0	58	0	0
T93	0	87	0	0
T94	0	87	0	0
T115	0	68	0	0
T119	0	6	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	4616	0	0
T3	120815	71	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	61	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	318	0	0
T48	0	38	0	0
T49	0	10	0	0
T86	0	56	0	0
T93	0	101	0	0
T94	0	44	0	0
T115	0	41	0	0
T119	0	6	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	4468	0	0
T3	120815	65	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	66	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	230	0	0
T48	0	36	0	0
T49	0	6	0	0
T86	0	93	0	0
T93	0	86	0	0
T115	0	56	0	0
T118	0	8	0	0
T119	0	7	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	4656	0	0
T3	120815	69	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	97	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	318	0	0
T48	0	17	0	0
T49	0	6	0	0
T86	0	83	0	0
T93	0	81	0	0
T94	0	62	0	0
T95	0	29	0	0
T115	0	78	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	4447	0	0
T3	120815	54	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	76	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	357	0	0
T48	0	25	0	0
T49	0	3	0	0
T86	0	51	0	0
T93	0	85	0	0
T94	0	88	0	0
T115	0	53	0	0
T119	0	4	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	4546	0	0
T3	120815	94	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	70	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	339	0	0
T48	0	37	0	0
T49	0	7	0	0
T86	0	62	0	0
T93	0	67	0	0
T115	0	52	0	0
T118	0	10	0	0
T119	0	6	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	4510	0	0
T3	120815	71	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	70	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	342	0	0
T48	0	23	0	0
T86	0	63	0	0
T93	0	88	0	0
T94	0	62	0	0
T95	0	42	0	0
T115	0	52	0	0
T119	0	8	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11615183	4303	0	0
T3	120815	53	0	0
T4	3849	0	0	0
T5	4561	0	0	0
T6	30133	0	0	0
T7	5258	0	0	0
T8	5766	0	0	0
T9	5219	0	0	0
T10	38544	86	0	0
T11	2719	0	0	0
T12	3754	0	0	0
T23	0	324	0	0
T48	0	35	0	0
T49	0	4	0	0
T86	0	61	0	0
T93	0	56	0	0
T115	0	55	0	0
T118	0	5	0	0
T119	0	4	0	0