Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	609558	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

368327

1

T2

1082

T3

56

T6

956

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	520495	1			T2	1500		T3	72		T5	1
values[0x0]	228442	1			T2	829		T3	42		T6	602
values[0x1]	228948	1			T2	871		T3	34		T6	620

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	511953	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

465932

1

T2

1398

T3

70

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3671	1			T2	14		T7	9		T11	1
valid_sources[0x01]	3945	1			T2	4		T3	1		T11	1
valid_sources[0x02]	3166	1			T2	10		T9	7		T11	2
valid_sources[0x03]	6329	1			T2	6		T6	8		T11	1
valid_sources[0x04]	3433	1			T2	7		T13	9		T23	3
valid_sources[0x05]	4154	1			T2	15		T9	33		T11	1
valid_sources[0x06]	3392	1			T2	10		T3	1		T8	1
valid_sources[0x07]	3271	1			T2	14		T8	1		T13	7
valid_sources[0x08]	3519	1			T2	9		T7	3		T8	1
valid_sources[0x09]	3152	1			T2	16		T7	6		T11	4
valid_sources[0x0a]	3267	1			T2	14		T7	1		T9	9
valid_sources[0x0b]	5866	1			T2	19		T13	23		T63	2
valid_sources[0x0c]	3316	1			T2	16		T7	5		T11	1
valid_sources[0x0d]	3992	1			T2	8		T8	1		T11	1
valid_sources[0x0e]	3480	1			T2	9		T9	10		T11	1
valid_sources[0x0f]	3254	1			T2	10		T11	1		T13	12
valid_sources[0x10]	5687	1			T2	11		T8	1		T13	6
valid_sources[0x11]	3197	1			T2	13		T7	16		T9	2
valid_sources[0x12]	4087	1			T2	13		T3	2		T6	6
valid_sources[0x13]	3527	1			T2	11		T3	1		T8	1
valid_sources[0x14]	3296	1			T2	4		T9	16		T13	10
valid_sources[0x15]	3022	1			T2	14		T8	2		T9	4
valid_sources[0x16]	3453	1			T2	15		T3	3		T13	32
valid_sources[0x17]	4208	1			T2	17		T7	3		T13	23
valid_sources[0x18]	3611	1			T2	9		T7	3		T13	5
valid_sources[0x19]	3960	1			T2	17		T3	2		T7	3
valid_sources[0x1a]	3651	1			T2	17		T3	3		T9	25
valid_sources[0x1b]	3469	1			T2	7		T6	1		T9	5
valid_sources[0x1c]	3440	1			T2	15		T8	5		T11	1
valid_sources[0x1d]	3327	1			T2	14		T9	1		T11	1
valid_sources[0x1e]	3535	1			T2	11		T8	3		T13	6
valid_sources[0x1f]	3647	1			T2	13		T3	4		T7	1
valid_sources[0x20]	3227	1			T2	14		T3	2		T6	9
valid_sources[0x21]	3875	1			T2	13		T8	5		T13	2
valid_sources[0x22]	4232	1			T2	10		T6	182		T7	18
valid_sources[0x23]	3659	1			T2	12		T11	1		T13	9
valid_sources[0x24]	3242	1			T2	21		T3	2		T11	3
valid_sources[0x25]	3547	1			T2	9		T6	9		T8	2
valid_sources[0x26]	4269	1			T2	16		T3	4		T7	6
valid_sources[0x27]	4406	1			T2	9		T7	16		T8	1
valid_sources[0x28]	3663	1			T2	16		T9	3		T11	1
valid_sources[0x29]	3574	1			T2	14		T6	4		T13	47
valid_sources[0x2a]	3968	1			T2	13		T7	1		T8	1
valid_sources[0x2b]	3904	1			T2	7		T7	6		T13	2
valid_sources[0x2c]	4774	1			T2	15		T8	11		T11	3
valid_sources[0x2d]	2946	1			T2	9		T3	1		T7	7
valid_sources[0x2e]	3338	1			T2	9		T11	3		T13	9
valid_sources[0x2f]	3674	1			T2	21		T11	4		T13	7
valid_sources[0x30]	2885	1			T2	11		T13	10		T23	1
valid_sources[0x31]	3321	1			T2	10		T3	1		T7	3
valid_sources[0x32]	3231	1			T2	10		T6	2		T8	3
valid_sources[0x33]	3845	1			T2	17		T3	2		T5	1
valid_sources[0x34]	7582	1			T2	2		T13	12		T24	1
valid_sources[0x35]	4711	1			T2	9		T8	4		T9	3
valid_sources[0x36]	3819	1			T2	8		T13	6		T47	1
valid_sources[0x37]	3880	1			T2	8		T3	1		T13	8
valid_sources[0x38]	3209	1			T2	11		T9	1		T11	1
valid_sources[0x39]	3975	1			T2	22		T7	8		T8	1
valid_sources[0x3a]	3607	1			T2	11		T8	1		T13	15
valid_sources[0x3b]	3993	1			T2	4		T6	129		T8	1
valid_sources[0x3c]	7678	1			T2	14		T8	3		T13	16
valid_sources[0x3d]	4106	1			T2	17		T3	2		T7	2
valid_sources[0x3e]	3748	1			T2	22		T13	17		T14	238
valid_sources[0x3f]	3177	1			T2	10		T9	2		T13	2
valid_sources[0x40]	6266	1			T2	11		T3	6		T11	2
valid_sources[0x41]	2992	1			T2	8		T13	19		T23	2
valid_sources[0x42]	4440	1			T2	4		T8	4		T11	1
valid_sources[0x43]	3126	1			T2	16		T9	12		T13	11
valid_sources[0x44]	3988	1			T2	11		T7	5		T9	8
valid_sources[0x45]	3581	1			T2	13		T3	8		T6	191
valid_sources[0x46]	3292	1			T2	10		T6	5		T7	5
valid_sources[0x47]	4126	1			T2	13		T7	16		T9	1
valid_sources[0x48]	7119	1			T2	20		T7	7		T8	5
valid_sources[0x49]	6137	1			T2	15		T9	6		T47	3
valid_sources[0x4a]	4141	1			T2	7		T3	4		T13	15
valid_sources[0x4b]	3193	1			T2	16		T8	10		T11	1
valid_sources[0x4c]	3209	1			T2	15		T8	3		T11	2
valid_sources[0x4d]	3560	1			T2	19		T13	1		T24	1
valid_sources[0x4e]	2991	1			T2	13		T6	3		T11	1
valid_sources[0x4f]	3963	1			T2	14		T13	1		T24	2
valid_sources[0x50]	3154	1			T2	12		T9	25		T13	1
valid_sources[0x51]	3095	1			T2	16		T13	3		T23	3
valid_sources[0x52]	3409	1			T2	10		T13	3		T23	1
valid_sources[0x53]	4013	1			T2	7		T8	7		T9	10
valid_sources[0x54]	3871	1			T2	22		T8	1		T9	26
valid_sources[0x55]	3012	1			T2	13		T13	6		T23	3
valid_sources[0x56]	3372	1			T2	9		T8	1		T13	7
valid_sources[0x57]	3507	1			T2	13		T9	10		T13	15
valid_sources[0x58]	3458	1			T2	6		T3	2		T9	7
valid_sources[0x59]	4459	1			T2	13		T6	392		T8	1
valid_sources[0x5a]	3424	1			T2	7		T3	3		T7	5
valid_sources[0x5b]	3873	1			T2	16		T7	13		T9	1
valid_sources[0x5c]	3664	1			T2	10		T13	11		T23	1
valid_sources[0x5d]	6570	1			T2	13		T7	1		T9	6
valid_sources[0x5e]	5873	1			T2	8		T7	10		T9	5
valid_sources[0x5f]	3967	1			T2	11		T3	9		T9	19
valid_sources[0x60]	4665	1			T2	18		T3	2		T7	2
valid_sources[0x61]	3381	1			T2	14		T3	2		T6	70
valid_sources[0x62]	2806	1			T2	14		T7	1		T8	5
valid_sources[0x63]	3393	1			T2	9		T3	2		T8	1
valid_sources[0x64]	3673	1			T2	13		T9	22		T11	1
valid_sources[0x65]	3590	1			T2	20		T7	1		T13	2
valid_sources[0x66]	4268	1			T2	4		T8	3		T11	4
valid_sources[0x67]	3020	1			T2	14		T6	3		T8	1
valid_sources[0x68]	4372	1			T2	23		T9	2		T13	26
valid_sources[0x69]	4574	1			T2	19		T7	2		T13	5
valid_sources[0x6a]	6167	1			T2	11		T3	1		T13	1
valid_sources[0x6b]	3253	1			T2	20		T3	5		T9	3
valid_sources[0x6c]	2984	1			T2	7		T3	1		T8	2
valid_sources[0x6d]	2805	1			T2	11		T3	2		T8	1
valid_sources[0x6e]	4256	1			T2	18		T11	2		T13	15
valid_sources[0x6f]	2948	1			T2	10		T8	7		T11	2
valid_sources[0x70]	4168	1			T2	12		T9	10		T13	2
valid_sources[0x71]	3824	1			T2	13		T3	1		T8	1
valid_sources[0x72]	3000	1			T2	12		T8	5		T13	13
valid_sources[0x73]	3328	1			T2	8		T11	1		T13	29
valid_sources[0x74]	3266	1			T2	9		T3	4		T8	1
valid_sources[0x75]	3377	1			T2	11		T11	2		T13	5
valid_sources[0x76]	3850	1			T2	17		T13	12		T23	1
valid_sources[0x77]	3078	1			T2	11		T7	2		T9	10
valid_sources[0x78]	3370	1			T2	11		T7	4		T8	5
valid_sources[0x79]	3253	1			T2	13		T6	2		T7	4
valid_sources[0x7a]	3320	1			T2	9		T6	1		T7	1
valid_sources[0x7b]	3439	1			T2	10		T7	3		T13	12
valid_sources[0x7c]	3253	1			T2	18		T8	1		T11	1
valid_sources[0x7d]	3396	1			T2	16		T8	2		T13	10
valid_sources[0x7e]	2971	1			T2	11		T13	11		T14	112
valid_sources[0x7f]	7579	1			T2	6		T11	1		T13	16
valid_sources[0x80]	4217	1			T2	9		T6	132		T7	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

244766

1

T2

662

T3

37

T6

672

values[0x0]

all_enables

biggest_size

80236

1

T2

267

T3

16

T6

189

values[0x1]

all_enables

biggest_size

43325

1

T2

153

T3

3

T6

95