Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T11
0	1	Covered	T6,T11,T13
1	0	Covered	T6,T7,T13

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T6,T7,T11
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54687086	9002	0	0
CascadeEffAonToRstPorAboveRise_A	54687086	9002	0	0
CascadeEffAonToRstPorIoAboveFall_A	52498387	9002	0	0
CascadeEffAonToRstPorIoAboveRise_A	52498387	9002	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26249844	9002	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26249844	9002	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13124755	9002	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13124755	9002	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26249890	9002	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26249890	9002	0	0
CascadeLcToLcAboveFall_A	54687086	21945	0	0
CascadeLcToLcAboveRise_A	54687086	21945	0	0
CascadeLcToLcAonAboveFall_A	1657083	21945	0	0
CascadeLcToLcAonAboveRise_A	1657083	21945	0	0
CascadeLcToLcShadowedAboveFall_A	54687086	21945	0	0
CascadeLcToLcShadowedAboveRise_A	54687086	21945	0	0
CascadePorToAonAboveFall_A	1657083	7213	0	0
CascadeSysToSysAboveFall_A	54687086	21945	0	0
CascadeSysToSysAboveRise_A	54687086	21945	0	0
ScanRstToAonRise_A	1657083	187	0	0
StablePorToAonRise_A	1657083	9002	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11668045	21945	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11668045	21945	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11668045	21945	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11668045	21945	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13124755	21945	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13124755	21945	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11668045	21945	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11668045	21945	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11668045	21945	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11668045	21945	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54687086	9002	0	0
T1	24277	8	0	0
T2	189597	27	0	0
T3	12679	1	0	0
T4	24300	8	0	0
T5	16115	2	0	0
T6	169984	15	0	0
T7	12480	2	0	0
T8	19583	1	0	0
T9	10997	1	0	0
T10	13925	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54687086	9002	0	0
T1	24277	8	0	0
T2	189597	27	0	0
T3	12679	1	0	0
T4	24300	8	0	0
T5	16115	2	0	0
T6	169984	15	0	0
T7	12480	2	0	0
T8	19583	1	0	0
T9	10997	1	0	0
T10	13925	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52498387	9002	0	0
T1	23316	8	0	0
T2	181961	27	0	0
T3	12172	1	0	0
T4	23319	8	0	0
T5	15469	2	0	0
T6	163185	15	0	0
T7	11981	2	0	0
T8	18800	1	0	0
T9	10558	1	0	0
T10	13368	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52498387	9002	0	0
T1	23316	8	0	0
T2	181961	27	0	0
T3	12172	1	0	0
T4	23319	8	0	0
T5	15469	2	0	0
T6	163185	15	0	0
T7	11981	2	0	0
T8	18800	1	0	0
T9	10558	1	0	0
T10	13368	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249844	9002	0	0
T1	11660	8	0	0
T2	90998	27	0	0
T3	6085	1	0	0
T4	11663	8	0	0
T5	7734	2	0	0
T6	81595	15	0	0
T7	5992	2	0	0
T8	9398	1	0	0
T9	5277	1	0	0
T10	6684	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249844	9002	0	0
T1	11660	8	0	0
T2	90998	27	0	0
T3	6085	1	0	0
T4	11663	8	0	0
T5	7734	2	0	0
T6	81595	15	0	0
T7	5992	2	0	0
T8	9398	1	0	0
T9	5277	1	0	0
T10	6684	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	9002	0	0
T1	5826	8	0	0
T2	45495	27	0	0
T3	3042	1	0	0
T4	5830	8	0	0
T5	3867	2	0	0
T6	40791	15	0	0
T7	2994	2	0	0
T8	4698	1	0	0
T9	2639	1	0	0
T10	3341	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	9002	0	0
T1	5826	8	0	0
T2	45495	27	0	0
T3	3042	1	0	0
T4	5830	8	0	0
T5	3867	2	0	0
T6	40791	15	0	0
T7	2994	2	0	0
T8	4698	1	0	0
T9	2639	1	0	0
T10	3341	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249890	9002	0	0
T1	11652	8	0	0
T2	90974	27	0	0
T3	6085	1	0	0
T4	11660	8	0	0
T5	7735	2	0	0
T6	81593	15	0	0
T7	5992	2	0	0
T8	9398	1	0	0
T9	5278	1	0	0
T10	6683	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249890	9002	0	0
T1	11652	8	0	0
T2	90974	27	0	0
T3	6085	1	0	0
T4	11660	8	0	0
T5	7735	2	0	0
T6	81593	15	0	0
T7	5992	2	0	0
T8	9398	1	0	0
T9	5278	1	0	0
T10	6683	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54687086	21945	0	0
T1	24277	8	0	0
T2	189597	102	0	0
T3	12679	9	0	0
T4	24300	8	0	0
T5	16115	2	0	0
T6	169984	55	0	0
T7	12480	6	0	0
T8	19583	15	0	0
T9	10997	1	0	0
T10	13925	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54687086	21945	0	0
T1	24277	8	0	0
T2	189597	102	0	0
T3	12679	9	0	0
T4	24300	8	0	0
T5	16115	2	0	0
T6	169984	55	0	0
T7	12480	6	0	0
T8	19583	15	0	0
T9	10997	1	0	0
T10	13925	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657083	21945	0	0
T1	731	8	0	0
T2	5701	102	0	0
T3	379	9	0	0
T4	730	8	0	0
T5	482	2	0	0
T6	5166	55	0	0
T7	372	6	0	0
T8	585	15	0	0
T9	329	1	0	0
T10	416	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657083	21945	0	0
T1	731	8	0	0
T2	5701	102	0	0
T3	379	9	0	0
T4	730	8	0	0
T5	482	2	0	0
T6	5166	55	0	0
T7	372	6	0	0
T8	585	15	0	0
T9	329	1	0	0
T10	416	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54687086	21945	0	0
T1	24277	8	0	0
T2	189597	102	0	0
T3	12679	9	0	0
T4	24300	8	0	0
T5	16115	2	0	0
T6	169984	55	0	0
T7	12480	6	0	0
T8	19583	15	0	0
T9	10997	1	0	0
T10	13925	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54687086	21945	0	0
T1	24277	8	0	0
T2	189597	102	0	0
T3	12679	9	0	0
T4	24300	8	0	0
T5	16115	2	0	0
T6	169984	55	0	0
T7	12480	6	0	0
T8	19583	15	0	0
T9	10997	1	0	0
T10	13925	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657083	7213	0	0
T1	731	8	0	0
T2	5701	27	0	0
T3	379	1	0	0
T4	730	8	0	0
T5	482	15	0	0
T6	5166	10	0	0
T7	372	1	0	0
T8	585	1	0	0
T9	329	1	0	0
T10	416	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54687086	21945	0	0
T1	24277	8	0	0
T2	189597	102	0	0
T3	12679	9	0	0
T4	24300	8	0	0
T5	16115	2	0	0
T6	169984	55	0	0
T7	12480	6	0	0
T8	19583	15	0	0
T9	10997	1	0	0
T10	13925	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54687086	21945	0	0
T1	24277	8	0	0
T2	189597	102	0	0
T3	12679	9	0	0
T4	24300	8	0	0
T5	16115	2	0	0
T6	169984	55	0	0
T7	12480	6	0	0
T8	19583	15	0	0
T9	10997	1	0	0
T10	13925	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657083	187	0	0
T13	4873	2	0	0
T14	4324	1	0	0
T15	357	0	0	0
T23	477	0	0	0
T24	281	0	0	0
T41	7084	0	0	0
T46	227	0	0	0
T47	591	0	0	0
T48	0	5	0	0
T61	339	0	0	0
T62	731	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T85	0	3	0	0
T87	0	6	0	0
T95	0	7	0	0
T130	0	1	0	0
T131	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657083	9002	0	0
T1	731	8	0	0
T2	5701	27	0	0
T3	379	1	0	0
T4	730	8	0	0
T5	482	2	0	0
T6	5166	15	0	0
T7	372	2	0	0
T8	585	1	0	0
T9	329	1	0	0
T10	416	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11668045	21945	0	0
T1	5282	8	0	0
T2	42514	102	0	0
T3	2471	9	0	0
T4	5287	8	0	0
T5	3776	2	0	0
T6	36772	55	0	0
T7	2704	6	0	0
T8	3704	15	0	0
T9	2572	1	0	0
T10	3251	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11668045	21945	0	0
T1	5282	8	0	0
T2	42514	102	0	0
T3	2471	9	0	0
T4	5287	8	0	0
T5	3776	2	0	0
T6	36772	55	0	0
T7	2704	6	0	0
T8	3704	15	0	0
T9	2572	1	0	0
T10	3251	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11668045	21945	0	0
T1	5282	8	0	0
T2	42514	102	0	0
T3	2471	9	0	0
T4	5287	8	0	0
T5	3776	2	0	0
T6	36772	55	0	0
T7	2704	6	0	0
T8	3704	15	0	0
T9	2572	1	0	0
T10	3251	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11668045	21945	0	0
T1	5282	8	0	0
T2	42514	102	0	0
T3	2471	9	0	0
T4	5287	8	0	0
T5	3776	2	0	0
T6	36772	55	0	0
T7	2704	6	0	0
T8	3704	15	0	0
T9	2572	1	0	0
T10	3251	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	21945	0	0
T1	5826	8	0	0
T2	45495	102	0	0
T3	3042	9	0	0
T4	5830	8	0	0
T5	3867	2	0	0
T6	40791	55	0	0
T7	2994	6	0	0
T8	4698	15	0	0
T9	2639	1	0	0
T10	3341	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	21945	0	0
T1	5826	8	0	0
T2	45495	102	0	0
T3	3042	9	0	0
T4	5830	8	0	0
T5	3867	2	0	0
T6	40791	55	0	0
T7	2994	6	0	0
T8	4698	15	0	0
T9	2639	1	0	0
T10	3341	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11668045	21945	0	0
T1	5282	8	0	0
T2	42514	102	0	0
T3	2471	9	0	0
T4	5287	8	0	0
T5	3776	2	0	0
T6	36772	55	0	0
T7	2704	6	0	0
T8	3704	15	0	0
T9	2572	1	0	0
T10	3251	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11668045	21945	0	0
T1	5282	8	0	0
T2	42514	102	0	0
T3	2471	9	0	0
T4	5287	8	0	0
T5	3776	2	0	0
T6	36772	55	0	0
T7	2704	6	0	0
T8	3704	15	0	0
T9	2572	1	0	0
T10	3251	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11668045	21945	0	0
T1	5282	8	0	0
T2	42514	102	0	0
T3	2471	9	0	0
T4	5287	8	0	0
T5	3776	2	0	0
T6	36772	55	0	0
T7	2704	6	0	0
T8	3704	15	0	0
T9	2572	1	0	0
T10	3251	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11668045	21945	0	0
T1	5282	8	0	0
T2	42514	102	0	0
T3	2471	9	0	0
T4	5287	8	0	0
T5	3776	2	0	0
T6	36772	55	0	0
T7	2704	6	0	0
T8	3704	15	0	0
T9	2572	1	0	0
T10	3251	1	0	0