Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T23
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T23
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T48
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T48
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13124755	13884	0	0
gen_assertions[0].RstEnOn_A	13124755	1123	0	0
gen_assertions[0].RstNOff_A	13124755	13884	0	0
gen_assertions[0].RstNOn_A	13124755	1123	0	0
gen_assertions[1].RstEnOff_A	52498387	12549	0	0
gen_assertions[1].RstEnOn_A	52498387	1065	0	0
gen_assertions[1].RstNOff_A	52498387	12549	0	0
gen_assertions[1].RstNOn_A	52498387	1065	0	0
gen_assertions[2].RstEnOff_A	26249844	12625	0	0
gen_assertions[2].RstEnOn_A	26249844	1067	0	0
gen_assertions[2].RstNOff_A	26249844	12625	0	0
gen_assertions[2].RstNOn_A	26249844	1067	0	0
gen_assertions[3].RstEnOff_A	26249890	12664	0	0
gen_assertions[3].RstEnOn_A	26249890	1107	0	0
gen_assertions[3].RstNOff_A	26249890	12664	0	0
gen_assertions[3].RstNOn_A	26249890	1107	0	0
gen_assertions[4].RstEnOff_A	1657083	21836	0	0
gen_assertions[4].RstEnOn_A	1657083	1148	0	0
gen_assertions[4].RstNOff_A	1657083	21836	0	0
gen_assertions[4].RstNOn_A	1657083	1148	0	0
gen_assertions[5].RstEnOff_A	13124755	14064	0	0
gen_assertions[5].RstEnOn_A	13124755	1154	0	0
gen_assertions[5].RstNOff_A	13124755	14064	0	0
gen_assertions[5].RstNOn_A	13124755	1154	0	0
gen_assertions[6].RstEnOff_A	13124755	14166	0	0
gen_assertions[6].RstEnOn_A	13124755	1264	0	0
gen_assertions[6].RstNOff_A	13124755	14166	0	0
gen_assertions[6].RstNOn_A	13124755	1264	0	0
gen_assertions[7].RstEnOff_A	13124755	14198	0	0
gen_assertions[7].RstEnOn_A	13124755	1300	0	0
gen_assertions[7].RstNOff_A	13124755	14198	0	0
gen_assertions[7].RstNOn_A	13124755	1300	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	13884	0	0
T2	45495	75	0	0
T3	3042	8	0	0
T4	5830	0	0	0
T5	3867	0	0	0
T6	40791	40	0	0
T7	2994	5	0	0
T8	4698	14	0	0
T9	2639	1	0	0
T10	3341	6	0	0
T11	2622	4	0	0
T13	0	31	0	0
T14	0	33	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	1123	0	0
T3	3042	1	0	0
T4	5830	0	0	0
T5	3867	0	0	0
T6	40791	0	0	0
T7	2994	1	0	0
T8	4698	1	0	0
T9	2639	1	0	0
T10	3341	6	0	0
T11	2622	0	0	0
T12	3362	0	0	0
T23	0	7	0	0
T48	0	8	0	0
T53	0	2	0	0
T57	0	1	0	0
T58	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	13884	0	0
T2	45495	75	0	0
T3	3042	8	0	0
T4	5830	0	0	0
T5	3867	0	0	0
T6	40791	40	0	0
T7	2994	5	0	0
T8	4698	14	0	0
T9	2639	1	0	0
T10	3341	6	0	0
T11	2622	4	0	0
T13	0	31	0	0
T14	0	33	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	1123	0	0
T3	3042	1	0	0
T4	5830	0	0	0
T5	3867	0	0	0
T6	40791	0	0	0
T7	2994	1	0	0
T8	4698	1	0	0
T9	2639	1	0	0
T10	3341	6	0	0
T11	2622	0	0	0
T12	3362	0	0	0
T23	0	7	0	0
T48	0	8	0	0
T53	0	2	0	0
T57	0	1	0	0
T58	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52498387	12549	0	0
T2	181961	70	0	0
T3	12172	7	0	0
T4	23319	0	0	0
T5	15469	0	0	0
T6	163185	35	0	0
T7	11981	4	0	0
T8	18800	14	0	0
T9	10558	2	0	0
T10	13368	5	0	0
T11	10496	4	0	0
T13	0	25	0	0
T14	0	30	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52498387	1065	0	0
T9	10558	2	0	0
T10	13368	5	0	0
T11	10496	0	0	0
T12	13453	0	0	0
T13	153758	0	0	0
T14	135296	0	0	0
T15	11484	0	0	0
T23	15292	5	0	0
T24	9028	0	0	0
T46	7334	0	0	0
T47	0	1	0	0
T48	0	7	0	0
T53	0	4	0	0
T57	0	1	0	0
T58	0	5	0	0
T59	0	4	0	0
T61	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52498387	12549	0	0
T2	181961	70	0	0
T3	12172	7	0	0
T4	23319	0	0	0
T5	15469	0	0	0
T6	163185	35	0	0
T7	11981	4	0	0
T8	18800	14	0	0
T9	10558	2	0	0
T10	13368	5	0	0
T11	10496	4	0	0
T13	0	25	0	0
T14	0	30	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52498387	1065	0	0
T9	10558	2	0	0
T10	13368	5	0	0
T11	10496	0	0	0
T12	13453	0	0	0
T13	153758	0	0	0
T14	135296	0	0	0
T15	11484	0	0	0
T23	15292	5	0	0
T24	9028	0	0	0
T46	7334	0	0	0
T47	0	1	0	0
T48	0	7	0	0
T53	0	4	0	0
T57	0	1	0	0
T58	0	5	0	0
T59	0	4	0	0
T61	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249844	12625	0	0
T2	90998	70	0	0
T3	6085	7	0	0
T4	11663	0	0	0
T5	7734	0	0	0
T6	81595	35	0	0
T7	5992	4	0	0
T8	9398	14	0	0
T9	5277	4	0	0
T10	6684	6	0	0
T11	5245	4	0	0
T13	0	25	0	0
T14	0	30	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249844	1067	0	0
T9	5277	4	0	0
T10	6684	6	0	0
T11	5245	0	0	0
T12	6725	0	0	0
T13	76889	0	0	0
T14	67649	0	0	0
T15	5742	0	0	0
T23	7646	2	0	0
T24	4515	0	0	0
T46	3666	0	0	0
T48	0	9	0	0
T53	0	4	0	0
T58	0	6	0	0
T59	0	5	0	0
T84	0	5	0	0
T85	0	34	0	0
T86	0	7	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249844	12625	0	0
T2	90998	70	0	0
T3	6085	7	0	0
T4	11663	0	0	0
T5	7734	0	0	0
T6	81595	35	0	0
T7	5992	4	0	0
T8	9398	14	0	0
T9	5277	4	0	0
T10	6684	6	0	0
T11	5245	4	0	0
T13	0	25	0	0
T14	0	30	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249844	1067	0	0
T9	5277	4	0	0
T10	6684	6	0	0
T11	5245	0	0	0
T12	6725	0	0	0
T13	76889	0	0	0
T14	67649	0	0	0
T15	5742	0	0	0
T23	7646	2	0	0
T24	4515	0	0	0
T46	3666	0	0	0
T48	0	9	0	0
T53	0	4	0	0
T58	0	6	0	0
T59	0	5	0	0
T84	0	5	0	0
T85	0	34	0	0
T86	0	7	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249890	12664	0	0
T2	90974	70	0	0
T3	6085	7	0	0
T4	11660	0	0	0
T5	7735	0	0	0
T6	81593	35	0	0
T7	5992	4	0	0
T8	9398	14	0	0
T9	5278	3	0	0
T10	6683	6	0	0
T11	5246	4	0	0
T13	0	25	0	0
T14	0	30	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249890	1107	0	0
T9	5278	3	0	0
T10	6683	6	0	0
T11	5246	0	0	0
T12	6725	0	0	0
T13	76880	0	0	0
T14	67651	0	0	0
T15	5742	0	0	0
T23	7646	0	0	0
T24	4515	0	0	0
T46	3667	0	0	0
T48	0	7	0	0
T53	0	6	0	0
T58	0	4	0	0
T59	0	5	0	0
T84	0	5	0	0
T85	0	30	0	0
T86	0	7	0	0
T87	0	10	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249890	12664	0	0
T2	90974	70	0	0
T3	6085	7	0	0
T4	11660	0	0	0
T5	7735	0	0	0
T6	81593	35	0	0
T7	5992	4	0	0
T8	9398	14	0	0
T9	5278	3	0	0
T10	6683	6	0	0
T11	5246	4	0	0
T13	0	25	0	0
T14	0	30	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249890	1107	0	0
T9	5278	3	0	0
T10	6683	6	0	0
T11	5246	0	0	0
T12	6725	0	0	0
T13	76880	0	0	0
T14	67651	0	0	0
T15	5742	0	0	0
T23	7646	0	0	0
T24	4515	0	0	0
T46	3667	0	0	0
T48	0	7	0	0
T53	0	6	0	0
T58	0	4	0	0
T59	0	5	0	0
T84	0	5	0	0
T85	0	30	0	0
T86	0	7	0	0
T87	0	10	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657083	21836	0	0
T1	731	3	0	0
T2	5701	91	0	0
T3	379	9	0	0
T4	730	3	0	0
T5	482	2	0	0
T6	5166	54	0	0
T7	372	7	0	0
T8	585	15	0	0
T9	329	6	0	0
T10	416	10	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657083	1148	0	0
T7	372	1	0	0
T8	585	0	0	0
T9	329	5	0	0
T10	416	9	0	0
T11	327	0	0	0
T12	420	0	0	0
T13	4873	0	0	0
T14	4324	0	0	0
T23	477	0	0	0
T24	281	0	0	0
T47	0	1	0	0
T48	0	6	0	0
T53	0	8	0	0
T58	0	6	0	0
T59	0	7	0	0
T61	0	1	0	0
T84	0	6	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657083	21836	0	0
T1	731	3	0	0
T2	5701	91	0	0
T3	379	9	0	0
T4	730	3	0	0
T5	482	2	0	0
T6	5166	54	0	0
T7	372	7	0	0
T8	585	15	0	0
T9	329	6	0	0
T10	416	10	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657083	1148	0	0
T7	372	1	0	0
T8	585	0	0	0
T9	329	5	0	0
T10	416	9	0	0
T11	327	0	0	0
T12	420	0	0	0
T13	4873	0	0	0
T14	4324	0	0	0
T23	477	0	0	0
T24	281	0	0	0
T47	0	1	0	0
T48	0	6	0	0
T53	0	8	0	0
T58	0	6	0	0
T59	0	7	0	0
T61	0	1	0	0
T84	0	6	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	14064	0	0
T2	45495	75	0	0
T3	3042	8	0	0
T4	5830	0	0	0
T5	3867	0	0	0
T6	40791	40	0	0
T7	2994	5	0	0
T8	4698	14	0	0
T9	2639	7	0	0
T10	3341	9	0	0
T11	2622	4	0	0
T13	0	31	0	0
T14	0	33	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	1154	0	0
T7	2994	1	0	0
T8	4698	0	0	0
T9	2639	7	0	0
T10	3341	9	0	0
T11	2622	0	0	0
T12	3362	0	0	0
T13	38446	0	0	0
T14	33820	0	0	0
T23	3822	0	0	0
T24	2256	0	0	0
T47	0	1	0	0
T48	0	8	0	0
T53	0	8	0	0
T58	0	7	0	0
T59	0	4	0	0
T84	0	8	0	0
T85	0	30	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	14064	0	0
T2	45495	75	0	0
T3	3042	8	0	0
T4	5830	0	0	0
T5	3867	0	0	0
T6	40791	40	0	0
T7	2994	5	0	0
T8	4698	14	0	0
T9	2639	7	0	0
T10	3341	9	0	0
T11	2622	4	0	0
T13	0	31	0	0
T14	0	33	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	1154	0	0
T7	2994	1	0	0
T8	4698	0	0	0
T9	2639	7	0	0
T10	3341	9	0	0
T11	2622	0	0	0
T12	3362	0	0	0
T13	38446	0	0	0
T14	33820	0	0	0
T23	3822	0	0	0
T24	2256	0	0	0
T47	0	1	0	0
T48	0	8	0	0
T53	0	8	0	0
T58	0	7	0	0
T59	0	4	0	0
T84	0	8	0	0
T85	0	30	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	14166	0	0
T2	45495	75	0	0
T3	3042	8	0	0
T4	5830	0	0	0
T5	3867	0	0	0
T6	40791	40	0	0
T7	2994	5	0	0
T8	4698	14	0	0
T9	2639	8	0	0
T10	3341	11	0	0
T11	2622	4	0	0
T13	0	31	0	0
T14	0	33	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	1264	0	0
T7	2994	1	0	0
T8	4698	0	0	0
T9	2639	8	0	0
T10	3341	11	0	0
T11	2622	0	0	0
T12	3362	0	0	0
T13	38446	0	0	0
T14	33820	0	0	0
T23	3822	0	0	0
T24	2256	0	0	0
T48	0	7	0	0
T53	0	9	0	0
T58	0	9	0	0
T59	0	6	0	0
T61	0	1	0	0
T84	0	8	0	0
T85	0	32	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	14166	0	0
T2	45495	75	0	0
T3	3042	8	0	0
T4	5830	0	0	0
T5	3867	0	0	0
T6	40791	40	0	0
T7	2994	5	0	0
T8	4698	14	0	0
T9	2639	8	0	0
T10	3341	11	0	0
T11	2622	4	0	0
T13	0	31	0	0
T14	0	33	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	1264	0	0
T7	2994	1	0	0
T8	4698	0	0	0
T9	2639	8	0	0
T10	3341	11	0	0
T11	2622	0	0	0
T12	3362	0	0	0
T13	38446	0	0	0
T14	33820	0	0	0
T23	3822	0	0	0
T24	2256	0	0	0
T48	0	7	0	0
T53	0	9	0	0
T58	0	9	0	0
T59	0	6	0	0
T61	0	1	0	0
T84	0	8	0	0
T85	0	32	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	14198	0	0
T2	45495	75	0	0
T3	3042	8	0	0
T4	5830	0	0	0
T5	3867	0	0	0
T6	40791	40	0	0
T7	2994	4	0	0
T8	4698	14	0	0
T9	2639	8	0	0
T10	3341	12	0	0
T11	2622	4	0	0
T13	0	31	0	0
T14	0	33	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	1300	0	0
T9	2639	8	0	0
T10	3341	12	0	0
T11	2622	0	0	0
T12	3362	0	0	0
T13	38446	0	0	0
T14	33820	0	0	0
T15	2870	0	0	0
T23	3822	0	0	0
T24	2256	0	0	0
T46	1832	0	0	0
T48	0	6	0	0
T53	0	10	0	0
T58	0	10	0	0
T59	0	7	0	0
T84	0	10	0	0
T85	0	34	0	0
T86	0	9	0	0
T87	0	12	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	14198	0	0
T2	45495	75	0	0
T3	3042	8	0	0
T4	5830	0	0	0
T5	3867	0	0	0
T6	40791	40	0	0
T7	2994	4	0	0
T8	4698	14	0	0
T9	2639	8	0	0
T10	3341	12	0	0
T11	2622	4	0	0
T13	0	31	0	0
T14	0	33	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124755	1300	0	0
T9	2639	8	0	0
T10	3341	12	0	0
T11	2622	0	0	0
T12	3362	0	0	0
T13	38446	0	0	0
T14	33820	0	0	0
T15	2870	0	0	0
T23	3822	0	0	0
T24	2256	0	0	0
T46	1832	0	0	0
T48	0	6	0	0
T53	0	10	0	0
T58	0	10	0	0
T59	0	7	0	0
T84	0	10	0	0
T85	0	34	0	0
T86	0	9	0	0
T87	0	12	0	0