Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12482527	9021	0	0
alert_regwen_rd_A	12482527	4949	0	0
cpu_regwen_rd_A	12482527	4817	0	0
sw_rst_ctrl_n_0_rd_A	12482527	8849	0	0
sw_rst_ctrl_n_1_rd_A	12482527	8816	0	0
sw_rst_ctrl_n_2_rd_A	12482527	8584	0	0
sw_rst_ctrl_n_3_rd_A	12482527	8980	0	0
sw_rst_ctrl_n_4_rd_A	12482527	8647	0	0
sw_rst_ctrl_n_5_rd_A	12482527	8717	0	0
sw_rst_ctrl_n_6_rd_A	12482527	8703	0	0
sw_rst_ctrl_n_7_rd_A	12482527	8711	0	0
sw_rst_regwen_0_rd_A	12482527	5293	0	0
sw_rst_regwen_1_rd_A	12482527	5422	0	0
sw_rst_regwen_2_rd_A	12482527	5405	0	0
sw_rst_regwen_3_rd_A	12482527	5320	0	0
sw_rst_regwen_4_rd_A	12482527	5276	0	0
sw_rst_regwen_5_rd_A	12482527	5622	0	0
sw_rst_regwen_6_rd_A	12482527	5415	0	0
sw_rst_regwen_7_rd_A	12482527	5517	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	9021	0	0
T66	3919	55	0	0
T67	3310	14	0	0
T70	4364	564	0	0
T71	19652	2	0	0
T72	21652	1	0	0
T88	2623	9	0	0
T89	3847	27	0	0
T90	2513	20	0	0
T91	3166	11	0	0
T93	2929	41	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	4949	0	0
T6	36772	58	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	43	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	59	0	0
T79	0	65	0	0
T97	0	63	0	0
T100	0	285	0	0
T101	0	53	0	0
T123	0	32	0	0
T124	0	244	0	0
T125	0	39	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	4817	0	0
T6	36772	46	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	48	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	83	0	0
T79	0	44	0	0
T97	0	72	0	0
T100	0	311	0	0
T101	0	23	0	0
T123	0	48	0	0
T124	0	225	0	0
T125	0	47	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	8849	0	0
T6	36772	57	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	34	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	95	0	0
T59	0	41	0	0
T79	0	78	0	0
T81	0	10	0	0
T86	0	190	0	0
T123	0	22	0	0
T126	0	3	0	0
T127	0	8	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	8816	0	0
T6	36772	48	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	69	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	98	0	0
T59	0	37	0	0
T79	0	62	0	0
T81	0	8	0	0
T86	0	165	0	0
T123	0	40	0	0
T126	0	8	0	0
T127	0	3	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	8584	0	0
T6	36772	38	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	60	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	67	0	0
T59	0	39	0	0
T79	0	45	0	0
T81	0	9	0	0
T86	0	140	0	0
T123	0	26	0	0
T126	0	14	0	0
T127	0	6	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	8980	0	0
T6	36772	59	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	63	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	70	0	0
T59	0	25	0	0
T79	0	51	0	0
T81	0	2	0	0
T86	0	152	0	0
T123	0	44	0	0
T126	0	9	0	0
T127	0	3	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	8647	0	0
T6	36772	44	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	73	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	76	0	0
T59	0	21	0	0
T79	0	60	0	0
T81	0	8	0	0
T86	0	120	0	0
T123	0	43	0	0
T126	0	5	0	0
T127	0	11	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	8717	0	0
T6	36772	55	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	52	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	52	0	0
T59	0	34	0	0
T79	0	63	0	0
T81	0	12	0	0
T86	0	155	0	0
T123	0	40	0	0
T126	0	11	0	0
T127	0	2	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	8703	0	0
T6	36772	22	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	66	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	97	0	0
T59	0	50	0	0
T79	0	73	0	0
T81	0	2	0	0
T86	0	166	0	0
T123	0	16	0	0
T126	0	17	0	0
T127	0	9	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	8711	0	0
T6	36772	54	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	52	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	74	0	0
T59	0	42	0	0
T79	0	67	0	0
T81	0	9	0	0
T86	0	207	0	0
T123	0	49	0	0
T126	0	17	0	0
T127	0	4	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	5293	0	0
T6	36772	38	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	58	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	74	0	0
T79	0	38	0	0
T81	0	3	0	0
T86	0	35	0	0
T97	0	53	0	0
T123	0	41	0	0
T126	0	10	0	0
T127	0	1	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	5422	0	0
T6	36772	44	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	42	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	104	0	0
T79	0	48	0	0
T81	0	5	0	0
T86	0	35	0	0
T97	0	72	0	0
T123	0	54	0	0
T126	0	2	0	0
T127	0	2	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	5405	0	0
T6	36772	44	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	58	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	98	0	0
T79	0	52	0	0
T81	0	6	0	0
T86	0	29	0	0
T97	0	60	0	0
T123	0	46	0	0
T126	0	4	0	0
T128	0	20	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	5320	0	0
T6	36772	35	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	37	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	72	0	0
T79	0	71	0	0
T86	0	42	0	0
T97	0	47	0	0
T123	0	36	0	0
T126	0	7	0	0
T127	0	3	0	0
T128	0	32	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	5276	0	0
T6	36772	52	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	62	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	81	0	0
T79	0	35	0	0
T86	0	42	0	0
T97	0	54	0	0
T123	0	27	0	0
T126	0	12	0	0
T127	0	7	0	0
T128	0	18	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	5622	0	0
T6	36772	53	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	61	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	88	0	0
T79	0	49	0	0
T86	0	41	0	0
T97	0	56	0	0
T123	0	57	0	0
T126	0	4	0	0
T127	0	6	0	0
T128	0	15	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	5415	0	0
T6	36772	43	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	63	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	86	0	0
T79	0	52	0	0
T81	0	10	0	0
T86	0	31	0	0
T97	0	60	0	0
T123	0	48	0	0
T126	0	5	0	0
T128	0	24	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12482527	5517	0	0
T6	36772	41	0	0
T7	2704	0	0	0
T8	3704	0	0	0
T9	2572	0	0	0
T10	3251	0	0	0
T11	2428	0	0	0
T12	3248	0	0	0
T13	34422	62	0	0
T14	29512	0	0	0
T23	2637	0	0	0
T40	0	102	0	0
T79	0	64	0	0
T81	0	8	0	0
T86	0	22	0	0
T97	0	50	0	0
T123	0	37	0	0
T126	0	9	0	0
T128	0	32	0	0