RSTMGR Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.730s 255.280us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.910s 129.237us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.940s 66.576us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 9.210s 1.984ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.660s 445.502us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.590s 134.489us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.940s 66.576us 20 20 100.00
rstmgr_csr_aliasing 2.660s 445.502us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.020s 203.697us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.730s 474.240us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.490s 241.609us 50 50 100.00
V2 reset_info rstmgr_reset 8.510s 2.270ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.510s 2.270ms 50 50 100.00
V2 alert_info rstmgr_reset 8.510s 2.270ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.510s 2.270ms 50 50 100.00
V2 stress_all rstmgr_stress_all 56.920s 16.418ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.940s 152.862us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 4.000s 647.624us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 4.000s 647.624us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.910s 129.237us 5 5 100.00
rstmgr_csr_rw 0.940s 66.576us 20 20 100.00
rstmgr_csr_aliasing 2.660s 445.502us 5 5 100.00
rstmgr_same_csr_outstanding 1.660s 192.610us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.910s 129.237us 5 5 100.00
rstmgr_csr_rw 0.940s 66.576us 20 20 100.00
rstmgr_csr_aliasing 2.660s 445.502us 5 5 100.00
rstmgr_same_csr_outstanding 1.660s 192.610us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 28.790s 18.611ms 5 5 100.00
rstmgr_tl_intg_err 3.490s 929.835us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 28.790s 18.611ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 28.790s 18.611ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.490s 929.835us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.340s 175.745us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.440s 2.375ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.180s 244.324us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 28.790s 18.611ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.940s 66.576us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.940s 66.576us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.44 99.40 99.31 99.87 -- 99.83 99.46 98.77

Past Results