Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	659509	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

396576

1

T1

1008

T2

77

T4

1108

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	564964	1			T1	1525		T2	90		T3	1
values[0x0]	245271	1			T1	561		T2	56		T4	831
values[0x1]	245850	1			T1	597		T2	40		T4	869

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	552993	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

503092

1

T1

1285

T2

88

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3340	1			T1	11		T4	13		T6	11
valid_sources[0x01]	4050	1			T1	36		T2	2		T4	11
valid_sources[0x02]	3023	1			T1	4		T4	9		T6	6
valid_sources[0x03]	6955	1			T1	44		T4	9		T6	23
valid_sources[0x04]	3498	1			T1	8		T4	16		T6	9
valid_sources[0x05]	4447	1			T2	2		T4	11		T6	13
valid_sources[0x06]	4449	1			T1	1		T4	17		T6	5
valid_sources[0x07]	3936	1			T1	10		T2	3		T4	16
valid_sources[0x08]	5222	1			T1	9		T4	21		T6	13
valid_sources[0x09]	3210	1			T1	9		T2	6		T4	12
valid_sources[0x0a]	6591	1			T1	1		T4	12		T6	8
valid_sources[0x0b]	3135	1			T1	22		T4	9		T6	3
valid_sources[0x0c]	3645	1			T4	14		T6	3		T8	4
valid_sources[0x0d]	4969	1			T1	8		T4	14		T6	14
valid_sources[0x0e]	3696	1			T1	24		T4	7		T6	11
valid_sources[0x0f]	5409	1			T1	25		T4	10		T6	17
valid_sources[0x10]	3923	1			T1	2		T4	24		T6	15
valid_sources[0x11]	3466	1			T1	6		T2	2		T4	10
valid_sources[0x12]	3965	1			T1	15		T4	13		T6	10
valid_sources[0x13]	3782	1			T1	15		T4	24		T6	10
valid_sources[0x14]	4990	1			T1	13		T4	14		T6	7
valid_sources[0x15]	7039	1			T1	9		T2	1		T4	14
valid_sources[0x16]	4149	1			T1	11		T2	4		T4	14
valid_sources[0x17]	4207	1			T1	20		T2	2		T4	6
valid_sources[0x18]	3373	1			T1	1		T4	15		T6	5
valid_sources[0x19]	3385	1			T1	8		T4	10		T6	5
valid_sources[0x1a]	6375	1			T1	21		T4	18		T6	2
valid_sources[0x1b]	3634	1			T1	7		T4	10		T6	20
valid_sources[0x1c]	3670	1			T1	15		T2	3		T4	18
valid_sources[0x1d]	3351	1			T1	1		T4	14		T6	13
valid_sources[0x1e]	3119	1			T1	28		T4	11		T6	5
valid_sources[0x1f]	3220	1			T1	12		T4	16		T6	13
valid_sources[0x20]	4025	1			T1	21		T4	14		T6	6
valid_sources[0x21]	6330	1			T1	9		T2	1		T4	7
valid_sources[0x22]	4787	1			T1	14		T4	14		T6	17
valid_sources[0x23]	3198	1			T1	32		T2	2		T4	11
valid_sources[0x24]	3311	1			T1	11		T4	14		T6	1
valid_sources[0x25]	3723	1			T1	33		T4	8		T6	14
valid_sources[0x26]	3375	1			T1	12		T4	6		T6	19
valid_sources[0x27]	4505	1			T4	11		T6	8		T8	1
valid_sources[0x28]	3886	1			T2	3		T4	15		T6	10
valid_sources[0x29]	3275	1			T1	8		T4	12		T6	24
valid_sources[0x2a]	3669	1			T1	17		T4	6		T6	13
valid_sources[0x2b]	3718	1			T1	5		T4	23		T6	19
valid_sources[0x2c]	3108	1			T4	17		T6	9		T22	17
valid_sources[0x2d]	6018	1			T1	20		T2	5		T4	11
valid_sources[0x2e]	4160	1			T1	22		T4	17		T6	5
valid_sources[0x2f]	3078	1			T4	15		T8	1		T20	1
valid_sources[0x30]	3213	1			T4	9		T6	22		T11	3
valid_sources[0x31]	4707	1			T1	35		T2	6		T4	13
valid_sources[0x32]	3007	1			T1	1		T4	12		T6	12
valid_sources[0x33]	3741	1			T4	10		T6	16		T11	1
valid_sources[0x34]	4197	1			T1	4		T4	10		T6	13
valid_sources[0x35]	4076	1			T1	2		T4	14		T6	25
valid_sources[0x36]	4637	1			T1	28		T4	13		T6	19
valid_sources[0x37]	3192	1			T2	1		T4	9		T6	5
valid_sources[0x38]	4430	1			T4	18		T6	5		T22	50
valid_sources[0x39]	4115	1			T1	21		T2	1		T4	16
valid_sources[0x3a]	3162	1			T1	2		T2	1		T4	8
valid_sources[0x3b]	3404	1			T2	6		T4	14		T6	11
valid_sources[0x3c]	3791	1			T1	8		T4	9		T6	9
valid_sources[0x3d]	3501	1			T1	17		T4	7		T6	12
valid_sources[0x3e]	6129	1			T1	16		T4	19		T6	11
valid_sources[0x3f]	3528	1			T4	10		T6	12		T8	2
valid_sources[0x40]	3898	1			T1	7		T4	9		T6	24
valid_sources[0x41]	3682	1			T4	11		T6	6		T8	4
valid_sources[0x42]	7447	1			T1	10		T2	2		T4	7
valid_sources[0x43]	4238	1			T1	5		T4	9		T6	19
valid_sources[0x44]	6071	1			T1	13		T4	9		T6	7
valid_sources[0x45]	3349	1			T1	14		T4	15		T6	11
valid_sources[0x46]	3803	1			T1	40		T2	5		T4	10
valid_sources[0x47]	5194	1			T1	18		T4	8		T6	17
valid_sources[0x48]	3203	1			T4	17		T6	18		T11	1
valid_sources[0x49]	5534	1			T4	12		T6	16		T11	2
valid_sources[0x4a]	5412	1			T1	54		T2	2		T4	12
valid_sources[0x4b]	3535	1			T1	26		T4	7		T6	27
valid_sources[0x4c]	3540	1			T1	1		T4	14		T6	16
valid_sources[0x4d]	4749	1			T1	16		T2	3		T4	14
valid_sources[0x4e]	4167	1			T1	14		T2	4		T4	16
valid_sources[0x4f]	3755	1			T1	11		T4	15		T6	13
valid_sources[0x50]	3887	1			T1	5		T4	10		T6	14
valid_sources[0x51]	4645	1			T1	6		T4	11		T6	4
valid_sources[0x52]	3350	1			T1	22		T4	14		T6	13
valid_sources[0x53]	2922	1			T2	2		T4	9		T6	15
valid_sources[0x54]	3273	1			T1	6		T4	13		T6	23
valid_sources[0x55]	4233	1			T1	1		T4	11		T6	13
valid_sources[0x56]	8203	1			T1	2		T4	14		T6	17
valid_sources[0x57]	3774	1			T4	18		T6	11		T22	32
valid_sources[0x58]	3496	1			T4	14		T6	22		T22	24
valid_sources[0x59]	3259	1			T1	7		T4	10		T6	9
valid_sources[0x5a]	3537	1			T1	23		T2	4		T4	13
valid_sources[0x5b]	3248	1			T4	14		T6	22		T8	3
valid_sources[0x5c]	3591	1			T1	10		T4	15		T6	9
valid_sources[0x5d]	4561	1			T4	19		T6	15		T22	47
valid_sources[0x5e]	4574	1			T4	22		T6	7		T8	1
valid_sources[0x5f]	3029	1			T1	13		T2	3		T4	6
valid_sources[0x60]	3572	1			T4	17		T6	4		T11	1
valid_sources[0x61]	4237	1			T4	11		T6	11		T22	31
valid_sources[0x62]	3902	1			T1	1		T4	8		T6	13
valid_sources[0x63]	3756	1			T1	7		T4	15		T6	19
valid_sources[0x64]	3876	1			T4	8		T6	6		T22	16
valid_sources[0x65]	5179	1			T1	6		T4	13		T6	8
valid_sources[0x66]	4653	1			T1	58		T4	17		T6	12
valid_sources[0x67]	3865	1			T4	7		T6	21		T20	1
valid_sources[0x68]	3806	1			T1	9		T2	2		T4	11
valid_sources[0x69]	3916	1			T1	37		T4	16		T6	9
valid_sources[0x6a]	3834	1			T4	14		T6	11		T22	40
valid_sources[0x6b]	3699	1			T1	45		T4	9		T6	9
valid_sources[0x6c]	3664	1			T1	5		T2	1		T4	8
valid_sources[0x6d]	5477	1			T1	1		T4	18		T6	7
valid_sources[0x6e]	4923	1			T1	1		T4	9		T6	7
valid_sources[0x6f]	3050	1			T1	3		T4	12		T6	20
valid_sources[0x70]	3736	1			T1	4		T4	10		T6	22
valid_sources[0x71]	4123	1			T4	14		T6	26		T8	6
valid_sources[0x72]	4538	1			T1	15		T4	19		T6	6
valid_sources[0x73]	3406	1			T4	14		T6	14		T8	1
valid_sources[0x74]	4886	1			T1	15		T2	3		T4	16
valid_sources[0x75]	4371	1			T1	1		T4	10		T6	5
valid_sources[0x76]	4560	1			T4	10		T6	8		T8	4
valid_sources[0x77]	4996	1			T1	15		T2	1		T4	14
valid_sources[0x78]	4098	1			T1	28		T4	7		T6	30
valid_sources[0x79]	3648	1			T1	30		T2	1		T4	12
valid_sources[0x7a]	6922	1			T1	31		T4	13		T6	10
valid_sources[0x7b]	3997	1			T1	1		T2	1		T4	14
valid_sources[0x7c]	3181	1			T1	7		T4	14		T6	21
valid_sources[0x7d]	3829	1			T1	35		T4	14		T6	25
valid_sources[0x7e]	3950	1			T1	3		T4	17		T6	9
valid_sources[0x7f]	3063	1			T1	19		T4	13		T6	20
valid_sources[0x80]	4260	1			T1	1		T2	1		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

265032

1

T1

716

T2

51

T4

672

values[0x0]

all_enables

biggest_size

85846

1

T1

197

T2

18

T4

276

values[0x1]

all_enables

biggest_size

45698

1

T1

95

T2

8

T4

160