Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	12723672	14077	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	12723672	129553	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	12723672	7658459	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	12723672	207572	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	12723672	14077	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	12723672	129553	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	12723672	7658459	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	12723672	207572	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	14077	0	0
T1	17398	32	0	0
T2	3116	10	0	0
T3	5088	0	0	0
T4	48852	75	0	0
T5	4702	0	0	0
T6	26056	75	0	0
T7	1910	0	0	0
T8	4124	4	0	0
T9	5180	0	0	0
T10	1932	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	29	0	0
T22	0	79	0	0
T23	0	14	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	129553	0	0
T1	17398	292	0	0
T2	3116	90	0	0
T3	5088	0	0	0
T4	48852	702	0	0
T5	4702	0	0	0
T6	26056	707	0	0
T7	1910	0	0	0
T8	4124	37	0	0
T9	5180	0	0	0
T10	1932	0	0	0
T11	0	45	0	0
T12	0	37	0	0
T21	0	262	0	0
T22	0	716	0	0
T23	0	126	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	7658459	0	0
T1	17398	7578	0	0
T2	3116	2316	0	0
T3	5088	839	0	0
T4	48852	31339	0	0
T5	4702	755	0	0
T6	26056	8690	0	0
T7	1910	1261	0	0
T8	4124	3113	0	0
T9	5180	861	0	0
T10	1932	1332	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	207572	0	0
T1	17398	467	0	0
T2	3116	154	0	0
T3	5088	0	0	0
T4	48852	1104	0	0
T5	4702	0	0	0
T6	26056	1150	0	0
T7	1910	0	0	0
T8	4124	63	0	0
T9	5180	0	0	0
T10	1932	0	0	0
T11	0	65	0	0
T12	0	75	0	0
T21	0	418	0	0
T22	0	1150	0	0
T23	0	204	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	14077	0	0
T1	17398	32	0	0
T2	3116	10	0	0
T3	5088	0	0	0
T4	48852	75	0	0
T5	4702	0	0	0
T6	26056	75	0	0
T7	1910	0	0	0
T8	4124	4	0	0
T9	5180	0	0	0
T10	1932	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	29	0	0
T22	0	79	0	0
T23	0	14	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	129553	0	0
T1	17398	292	0	0
T2	3116	90	0	0
T3	5088	0	0	0
T4	48852	702	0	0
T5	4702	0	0	0
T6	26056	707	0	0
T7	1910	0	0	0
T8	4124	37	0	0
T9	5180	0	0	0
T10	1932	0	0	0
T11	0	45	0	0
T12	0	37	0	0
T21	0	262	0	0
T22	0	716	0	0
T23	0	126	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	7658459	0	0
T1	17398	7578	0	0
T2	3116	2316	0	0
T3	5088	839	0	0
T4	48852	31339	0	0
T5	4702	755	0	0
T6	26056	8690	0	0
T7	1910	1261	0	0
T8	4124	3113	0	0
T9	5180	861	0	0
T10	1932	1332	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	207572	0	0
T1	17398	467	0	0
T2	3116	154	0	0
T3	5088	0	0	0
T4	48852	1104	0	0
T5	4702	0	0	0
T6	26056	1150	0	0
T7	1910	0	0	0
T8	4124	63	0	0
T9	5180	0	0	0
T10	1932	0	0	0
T11	0	65	0	0
T12	0	75	0	0
T21	0	418	0	0
T22	0	1150	0	0
T23	0	204	0	0