Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T12
0	1	Covered	T1,T8,T12
1	0	Covered	T1,T21,T22

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T8,T12
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	59679324	9372	0	0
CascadeEffAonToRstPorAboveRise_A	59679324	9372	0	0
CascadeEffAonToRstPorIoAboveFall_A	57290300	9372	0	0
CascadeEffAonToRstPorIoAboveRise_A	57290300	9372	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	28646283	9372	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	28646283	9372	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	14322794	9372	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	14322794	9372	0	0
CascadeEffAonToRstPorUcbAboveFall_A	28646144	9372	0	0
CascadeEffAonToRstPorUcbAboveRise_A	28646144	9372	0	0
CascadeLcToLcAboveFall_A	59679324	23449	0	0
CascadeLcToLcAboveRise_A	59679324	23449	0	0
CascadeLcToLcAonAboveFall_A	1808764	23449	0	0
CascadeLcToLcAonAboveRise_A	1808764	23449	0	0
CascadeLcToLcShadowedAboveFall_A	59679324	23449	0	0
CascadeLcToLcShadowedAboveRise_A	59679324	23449	0	0
CascadePorToAonAboveFall_A	1808764	7409	0	0
CascadeSysToSysAboveFall_A	59679324	23449	0	0
CascadeSysToSysAboveRise_A	59679324	23449	0	0
ScanRstToAonRise_A	1808764	221	0	0
StablePorToAonRise_A	1808764	9372	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12723672	23449	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12723672	23449	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12723672	23449	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12723672	23449	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	14322794	23449	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	14322794	23449	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12723672	23449	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12723672	23449	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12723672	23449	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12723672	23449	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	9372	0	0
T1	92058	20	0	0
T2	16396	1	0	0
T3	21481	2	0	0
T4	216592	27	0	0
T5	19971	2	0	0
T6	121551	27	0	0
T7	8039	1	0	0
T8	17994	2	0	0
T9	21864	2	0	0
T10	8330	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	9372	0	0
T1	92058	20	0	0
T2	16396	1	0	0
T3	21481	2	0	0
T4	216592	27	0	0
T5	19971	2	0	0
T6	121551	27	0	0
T7	8039	1	0	0
T8	17994	2	0	0
T9	21864	2	0	0
T10	8330	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57290300	9372	0	0
T1	88358	20	0	0
T2	15740	1	0	0
T3	20621	2	0	0
T4	207934	27	0	0
T5	19171	2	0	0
T6	116693	27	0	0
T7	7718	1	0	0
T8	17269	2	0	0
T9	20988	2	0	0
T10	7997	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57290300	9372	0	0
T1	88358	20	0	0
T2	15740	1	0	0
T3	20621	2	0	0
T4	207934	27	0	0
T5	19171	2	0	0
T6	116693	27	0	0
T7	7718	1	0	0
T8	17269	2	0	0
T9	20988	2	0	0
T10	7997	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646283	9372	0	0
T1	44191	20	0	0
T2	7870	1	0	0
T3	10310	2	0	0
T4	103987	27	0	0
T5	9585	2	0	0
T6	58345	27	0	0
T7	3857	1	0	0
T8	8637	2	0	0
T9	10494	2	0	0
T10	3998	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646283	9372	0	0
T1	44191	20	0	0
T2	7870	1	0	0
T3	10310	2	0	0
T4	103987	27	0	0
T5	9585	2	0	0
T6	58345	27	0	0
T7	3857	1	0	0
T8	8637	2	0	0
T9	10494	2	0	0
T10	3998	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	9372	0	0
T1	22090	20	0	0
T2	3933	1	0	0
T3	5154	2	0	0
T4	51988	27	0	0
T5	4792	2	0	0
T6	29166	27	0	0
T7	1928	1	0	0
T8	4317	2	0	0
T9	5246	2	0	0
T10	1998	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	9372	0	0
T1	22090	20	0	0
T2	3933	1	0	0
T3	5154	2	0	0
T4	51988	27	0	0
T5	4792	2	0	0
T6	29166	27	0	0
T7	1928	1	0	0
T8	4317	2	0	0
T9	5246	2	0	0
T10	1998	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646144	9372	0	0
T1	44181	20	0	0
T2	7870	1	0	0
T3	10310	2	0	0
T4	103954	27	0	0
T5	9586	2	0	0
T6	58341	27	0	0
T7	3857	1	0	0
T8	8634	2	0	0
T9	10495	2	0	0
T10	3997	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646144	9372	0	0
T1	44181	20	0	0
T2	7870	1	0	0
T3	10310	2	0	0
T4	103954	27	0	0
T5	9586	2	0	0
T6	58341	27	0	0
T7	3857	1	0	0
T8	8634	2	0	0
T9	10495	2	0	0
T10	3997	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	23449	0	0
T1	92058	52	0	0
T2	16396	11	0	0
T3	21481	2	0	0
T4	216592	102	0	0
T5	19971	2	0	0
T6	121551	102	0	0
T7	8039	1	0	0
T8	17994	6	0	0
T9	21864	2	0	0
T10	8330	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	23449	0	0
T1	92058	52	0	0
T2	16396	11	0	0
T3	21481	2	0	0
T4	216592	102	0	0
T5	19971	2	0	0
T6	121551	102	0	0
T7	8039	1	0	0
T8	17994	6	0	0
T9	21864	2	0	0
T10	8330	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	23449	0	0
T1	2812	52	0	0
T2	490	11	0	0
T3	643	2	0	0
T4	6513	102	0	0
T5	597	2	0	0
T6	3662	102	0	0
T7	239	1	0	0
T8	538	6	0	0
T9	654	2	0	0
T10	248	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	23449	0	0
T1	2812	52	0	0
T2	490	11	0	0
T3	643	2	0	0
T4	6513	102	0	0
T5	597	2	0	0
T6	3662	102	0	0
T7	239	1	0	0
T8	538	6	0	0
T9	654	2	0	0
T10	248	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	23449	0	0
T1	92058	52	0	0
T2	16396	11	0	0
T3	21481	2	0	0
T4	216592	102	0	0
T5	19971	2	0	0
T6	121551	102	0	0
T7	8039	1	0	0
T8	17994	6	0	0
T9	21864	2	0	0
T10	8330	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	23449	0	0
T1	92058	52	0	0
T2	16396	11	0	0
T3	21481	2	0	0
T4	216592	102	0	0
T5	19971	2	0	0
T6	121551	102	0	0
T7	8039	1	0	0
T8	17994	6	0	0
T9	21864	2	0	0
T10	8330	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	7409	0	0
T1	2812	13	0	0
T2	490	1	0	0
T3	643	20	0	0
T4	6513	27	0	0
T5	597	20	0	0
T6	3662	27	0	0
T7	239	1	0	0
T8	538	1	0	0
T9	654	19	0	0
T10	248	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	23449	0	0
T1	92058	52	0	0
T2	16396	11	0	0
T3	21481	2	0	0
T4	216592	102	0	0
T5	19971	2	0	0
T6	121551	102	0	0
T7	8039	1	0	0
T8	17994	6	0	0
T9	21864	2	0	0
T10	8330	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	23449	0	0
T1	92058	52	0	0
T2	16396	11	0	0
T3	21481	2	0	0
T4	216592	102	0	0
T5	19971	2	0	0
T6	121551	102	0	0
T7	8039	1	0	0
T8	17994	6	0	0
T9	21864	2	0	0
T10	8330	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	221	0	0
T1	2812	1	0	0
T2	490	0	0	0
T3	643	0	0	0
T4	6513	0	0	0
T5	597	0	0	0
T6	3662	0	0	0
T7	239	0	0	0
T8	538	0	0	0
T9	654	0	0	0
T10	248	0	0	0
T22	0	4	0	0
T37	0	2	0	0
T52	0	1	0	0
T53	0	6	0	0
T80	0	8	0	0
T86	0	2	0	0
T94	0	14	0	0
T114	0	1	0	0
T115	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	9372	0	0
T1	2812	20	0	0
T2	490	1	0	0
T3	643	2	0	0
T4	6513	27	0	0
T5	597	2	0	0
T6	3662	27	0	0
T7	239	1	0	0
T8	538	2	0	0
T9	654	2	0	0
T10	248	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	23449	0	0
T1	17398	52	0	0
T2	3116	11	0	0
T3	5088	2	0	0
T4	48852	102	0	0
T5	4702	2	0	0
T6	26056	102	0	0
T7	1910	1	0	0
T8	4124	6	0	0
T9	5180	2	0	0
T10	1932	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	23449	0	0
T1	17398	52	0	0
T2	3116	11	0	0
T3	5088	2	0	0
T4	48852	102	0	0
T5	4702	2	0	0
T6	26056	102	0	0
T7	1910	1	0	0
T8	4124	6	0	0
T9	5180	2	0	0
T10	1932	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	23449	0	0
T1	17398	52	0	0
T2	3116	11	0	0
T3	5088	2	0	0
T4	48852	102	0	0
T5	4702	2	0	0
T6	26056	102	0	0
T7	1910	1	0	0
T8	4124	6	0	0
T9	5180	2	0	0
T10	1932	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	23449	0	0
T1	17398	52	0	0
T2	3116	11	0	0
T3	5088	2	0	0
T4	48852	102	0	0
T5	4702	2	0	0
T6	26056	102	0	0
T7	1910	1	0	0
T8	4124	6	0	0
T9	5180	2	0	0
T10	1932	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	23449	0	0
T1	22090	52	0	0
T2	3933	11	0	0
T3	5154	2	0	0
T4	51988	102	0	0
T5	4792	2	0	0
T6	29166	102	0	0
T7	1928	1	0	0
T8	4317	6	0	0
T9	5246	2	0	0
T10	1998	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	23449	0	0
T1	22090	52	0	0
T2	3933	11	0	0
T3	5154	2	0	0
T4	51988	102	0	0
T5	4792	2	0	0
T6	29166	102	0	0
T7	1928	1	0	0
T8	4317	6	0	0
T9	5246	2	0	0
T10	1998	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	23449	0	0
T1	17398	52	0	0
T2	3116	11	0	0
T3	5088	2	0	0
T4	48852	102	0	0
T5	4702	2	0	0
T6	26056	102	0	0
T7	1910	1	0	0
T8	4124	6	0	0
T9	5180	2	0	0
T10	1932	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	23449	0	0
T1	17398	52	0	0
T2	3116	11	0	0
T3	5088	2	0	0
T4	48852	102	0	0
T5	4702	2	0	0
T6	26056	102	0	0
T7	1910	1	0	0
T8	4124	6	0	0
T9	5180	2	0	0
T10	1932	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	23449	0	0
T1	17398	52	0	0
T2	3116	11	0	0
T3	5088	2	0	0
T4	48852	102	0	0
T5	4702	2	0	0
T6	26056	102	0	0
T7	1910	1	0	0
T8	4124	6	0	0
T9	5180	2	0	0
T10	1932	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723672	23449	0	0
T1	17398	52	0	0
T2	3116	11	0	0
T3	5088	2	0	0
T4	48852	102	0	0
T5	4702	2	0	0
T6	26056	102	0	0
T7	1910	1	0	0
T8	4124	6	0	0
T9	5180	2	0	0
T10	1932	1	0	0