Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T11,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T60,T61
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T22,T61
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T61,T86
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T61,T86
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T60,T61
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T22,T61
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T61,T86
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	14322794	14972	0	0
gen_assertions[0].RstEnOn_A	14322794	1065	0	0
gen_assertions[0].RstNOff_A	14322794	14972	0	0
gen_assertions[0].RstNOn_A	14322794	1065	0	0
gen_assertions[1].RstEnOff_A	57290300	13655	0	0
gen_assertions[1].RstEnOn_A	57290300	1041	0	0
gen_assertions[1].RstNOff_A	57290300	13655	0	0
gen_assertions[1].RstNOn_A	57290300	1041	0	0
gen_assertions[2].RstEnOff_A	28646283	13710	0	0
gen_assertions[2].RstEnOn_A	28646283	1061	0	0
gen_assertions[2].RstNOff_A	28646283	13710	0	0
gen_assertions[2].RstNOn_A	28646283	1061	0	0
gen_assertions[3].RstEnOff_A	28646144	13739	0	0
gen_assertions[3].RstEnOn_A	28646144	1087	0	0
gen_assertions[3].RstNOff_A	28646144	13739	0	0
gen_assertions[3].RstNOn_A	28646144	1087	0	0
gen_assertions[4].RstEnOff_A	1808764	23328	0	0
gen_assertions[4].RstEnOn_A	1808764	1145	0	0
gen_assertions[4].RstNOff_A	1808764	23328	0	0
gen_assertions[4].RstNOn_A	1808764	1145	0	0
gen_assertions[5].RstEnOff_A	14322794	15226	0	0
gen_assertions[5].RstEnOn_A	14322794	1177	0	0
gen_assertions[5].RstNOff_A	14322794	15226	0	0
gen_assertions[5].RstNOn_A	14322794	1177	0	0
gen_assertions[6].RstEnOff_A	14322794	15274	0	0
gen_assertions[6].RstEnOn_A	14322794	1238	0	0
gen_assertions[6].RstNOff_A	14322794	15274	0	0
gen_assertions[6].RstNOn_A	14322794	1238	0	0
gen_assertions[7].RstEnOff_A	14322794	15328	0	0
gen_assertions[7].RstEnOn_A	14322794	1280	0	0
gen_assertions[7].RstNOff_A	14322794	15328	0	0
gen_assertions[7].RstNOn_A	14322794	1280	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	14972	0	0
T1	22090	32	0	0
T2	3933	10	0	0
T3	5154	0	0	0
T4	51988	75	0	0
T5	4792	0	0	0
T6	29166	75	0	0
T7	1928	0	0	0
T8	4317	4	0	0
T9	5246	0	0	0
T10	1998	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	29	0	0
T22	0	95	0	0
T23	0	14	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	1065	0	0
T2	3933	1	0	0
T3	5154	0	0	0
T4	51988	0	0	0
T5	4792	0	0	0
T6	29166	0	0	0
T7	1928	0	0	0
T8	4317	0	0	0
T9	5246	0	0	0
T10	1998	0	0	0
T11	2806	1	0	0
T22	0	18	0	0
T23	0	4	0	0
T60	0	1	0	0
T61	0	5	0	0
T62	0	6	0	0
T63	0	6	0	0
T86	0	22	0	0
T89	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	14972	0	0
T1	22090	32	0	0
T2	3933	10	0	0
T3	5154	0	0	0
T4	51988	75	0	0
T5	4792	0	0	0
T6	29166	75	0	0
T7	1928	0	0	0
T8	4317	4	0	0
T9	5246	0	0	0
T10	1998	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	29	0	0
T22	0	95	0	0
T23	0	14	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	1065	0	0
T2	3933	1	0	0
T3	5154	0	0	0
T4	51988	0	0	0
T5	4792	0	0	0
T6	29166	0	0	0
T7	1928	0	0	0
T8	4317	0	0	0
T9	5246	0	0	0
T10	1998	0	0	0
T11	2806	1	0	0
T22	0	18	0	0
T23	0	4	0	0
T60	0	1	0	0
T61	0	5	0	0
T62	0	6	0	0
T63	0	6	0	0
T86	0	22	0	0
T89	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57290300	13655	0	0
T1	88358	29	0	0
T2	15740	10	0	0
T3	20621	0	0	0
T4	207934	67	0	0
T5	19171	0	0	0
T6	116693	71	0	0
T7	7718	0	0	0
T8	17269	4	0	0
T9	20988	0	0	0
T10	7997	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	25	0	0
T22	0	84	0	0
T23	0	14	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57290300	1041	0	0
T22	453506	12	0	0
T23	22792	0	0	0
T24	23421	0	0	0
T53	0	16	0	0
T54	0	2	0	0
T56	5744	0	0	0
T57	8453	0	0	0
T60	24818	1	0	0
T61	33984	7	0	0
T62	0	10	0	0
T63	0	9	0	0
T85	23336	0	0	0
T86	0	22	0	0
T89	0	6	0	0
T90	0	1	0	0
T91	8396	0	0	0
T92	6523	0	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57290300	13655	0	0
T1	88358	29	0	0
T2	15740	10	0	0
T3	20621	0	0	0
T4	207934	67	0	0
T5	19171	0	0	0
T6	116693	71	0	0
T7	7718	0	0	0
T8	17269	4	0	0
T9	20988	0	0	0
T10	7997	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	25	0	0
T22	0	84	0	0
T23	0	14	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57290300	1041	0	0
T22	453506	12	0	0
T23	22792	0	0	0
T24	23421	0	0	0
T53	0	16	0	0
T54	0	2	0	0
T56	5744	0	0	0
T57	8453	0	0	0
T60	24818	1	0	0
T61	33984	7	0	0
T62	0	10	0	0
T63	0	9	0	0
T85	23336	0	0	0
T86	0	22	0	0
T89	0	6	0	0
T90	0	1	0	0
T91	8396	0	0	0
T92	6523	0	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646283	13710	0	0
T1	44191	29	0	0
T2	7870	10	0	0
T3	10310	0	0	0
T4	103987	67	0	0
T5	9585	0	0	0
T6	58345	71	0	0
T7	3857	0	0	0
T8	8637	4	0	0
T9	10494	0	0	0
T10	3998	0	0	0
T11	0	4	0	0
T12	0	5	0	0
T21	0	25	0	0
T22	0	87	0	0
T23	0	14	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646283	1061	0	0
T12	12112	1	0	0
T21	45248	0	0	0
T22	226767	16	0	0
T23	11395	0	0	0
T24	11704	0	0	0
T53	0	20	0	0
T54	0	5	0	0
T60	12405	0	0	0
T61	16990	9	0	0
T62	0	7	0	0
T63	0	9	0	0
T85	11668	0	0	0
T86	0	19	0	0
T89	0	6	0	0
T91	4198	0	0	0
T92	3262	0	0	0
T93	0	7	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646283	13710	0	0
T1	44191	29	0	0
T2	7870	10	0	0
T3	10310	0	0	0
T4	103987	67	0	0
T5	9585	0	0	0
T6	58345	71	0	0
T7	3857	0	0	0
T8	8637	4	0	0
T9	10494	0	0	0
T10	3998	0	0	0
T11	0	4	0	0
T12	0	5	0	0
T21	0	25	0	0
T22	0	87	0	0
T23	0	14	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646283	1061	0	0
T12	12112	1	0	0
T21	45248	0	0	0
T22	226767	16	0	0
T23	11395	0	0	0
T24	11704	0	0	0
T53	0	20	0	0
T54	0	5	0	0
T60	12405	0	0	0
T61	16990	9	0	0
T62	0	7	0	0
T63	0	9	0	0
T85	11668	0	0	0
T86	0	19	0	0
T89	0	6	0	0
T91	4198	0	0	0
T92	3262	0	0	0
T93	0	7	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646144	13739	0	0
T1	44181	29	0	0
T2	7870	10	0	0
T3	10310	0	0	0
T4	103954	67	0	0
T5	9586	0	0	0
T6	58341	71	0	0
T7	3857	0	0	0
T8	8634	4	0	0
T9	10495	0	0	0
T10	3997	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	25	0	0
T22	0	88	0	0
T23	0	14	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646144	1087	0	0
T22	226739	17	0	0
T23	11395	0	0	0
T24	11703	0	0	0
T53	0	14	0	0
T54	0	4	0	0
T56	2870	0	0	0
T57	4226	0	0	0
T60	12408	0	0	0
T61	16991	7	0	0
T62	0	13	0	0
T63	0	7	0	0
T85	11662	0	0	0
T86	0	18	0	0
T89	0	6	0	0
T91	4197	0	0	0
T92	3262	0	0	0
T93	0	7	0	0
T94	0	16	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646144	13739	0	0
T1	44181	29	0	0
T2	7870	10	0	0
T3	10310	0	0	0
T4	103954	67	0	0
T5	9586	0	0	0
T6	58341	71	0	0
T7	3857	0	0	0
T8	8634	4	0	0
T9	10495	0	0	0
T10	3997	0	0	0
T11	0	4	0	0
T12	0	4	0	0
T21	0	25	0	0
T22	0	88	0	0
T23	0	14	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646144	1087	0	0
T22	226739	17	0	0
T23	11395	0	0	0
T24	11703	0	0	0
T53	0	14	0	0
T54	0	4	0	0
T56	2870	0	0	0
T57	4226	0	0	0
T60	12408	0	0	0
T61	16991	7	0	0
T62	0	13	0	0
T63	0	7	0	0
T85	11662	0	0	0
T86	0	18	0	0
T89	0	6	0	0
T91	4197	0	0	0
T92	3262	0	0	0
T93	0	7	0	0
T94	0	16	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	23328	0	0
T1	2812	52	0	0
T2	490	11	0	0
T3	643	2	0	0
T4	6513	97	0	0
T5	597	2	0	0
T6	3662	75	0	0
T7	239	1	0	0
T8	538	6	0	0
T9	654	2	0	0
T10	248	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	1145	0	0
T22	14286	12	0	0
T23	710	0	0	0
T24	733	0	0	0
T53	0	14	0	0
T54	0	8	0	0
T56	178	0	0	0
T57	264	0	0	0
T60	775	0	0	0
T61	1060	8	0	0
T62	0	10	0	0
T63	0	12	0	0
T85	730	0	0	0
T86	0	16	0	0
T89	0	10	0	0
T90	0	1	0	0
T91	261	0	0	0
T92	202	0	0	0
T93	0	9	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	23328	0	0
T1	2812	52	0	0
T2	490	11	0	0
T3	643	2	0	0
T4	6513	97	0	0
T5	597	2	0	0
T6	3662	75	0	0
T7	239	1	0	0
T8	538	6	0	0
T9	654	2	0	0
T10	248	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	1145	0	0
T22	14286	12	0	0
T23	710	0	0	0
T24	733	0	0	0
T53	0	14	0	0
T54	0	8	0	0
T56	178	0	0	0
T57	264	0	0	0
T60	775	0	0	0
T61	1060	8	0	0
T62	0	10	0	0
T63	0	12	0	0
T85	730	0	0	0
T86	0	16	0	0
T89	0	10	0	0
T90	0	1	0	0
T91	261	0	0	0
T92	202	0	0	0
T93	0	9	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	15226	0	0
T1	22090	32	0	0
T2	3933	10	0	0
T3	5154	0	0	0
T4	51988	75	0	0
T5	4792	0	0	0
T6	29166	75	0	0
T7	1928	0	0	0
T8	4317	4	0	0
T9	5246	0	0	0
T10	1998	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	29	0	0
T22	0	95	0	0
T23	0	14	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	1177	0	0
T22	113383	18	0	0
T23	5697	0	0	0
T24	5852	0	0	0
T53	0	17	0	0
T54	0	7	0	0
T56	1434	0	0	0
T57	2112	0	0	0
T60	6203	1	0	0
T61	8494	12	0	0
T62	0	11	0	0
T63	0	12	0	0
T85	5827	0	0	0
T86	0	18	0	0
T89	0	10	0	0
T91	2098	0	0	0
T92	1630	0	0	0
T93	0	10	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	15226	0	0
T1	22090	32	0	0
T2	3933	10	0	0
T3	5154	0	0	0
T4	51988	75	0	0
T5	4792	0	0	0
T6	29166	75	0	0
T7	1928	0	0	0
T8	4317	4	0	0
T9	5246	0	0	0
T10	1998	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	29	0	0
T22	0	95	0	0
T23	0	14	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	1177	0	0
T22	113383	18	0	0
T23	5697	0	0	0
T24	5852	0	0	0
T53	0	17	0	0
T54	0	7	0	0
T56	1434	0	0	0
T57	2112	0	0	0
T60	6203	1	0	0
T61	8494	12	0	0
T62	0	11	0	0
T63	0	12	0	0
T85	5827	0	0	0
T86	0	18	0	0
T89	0	10	0	0
T91	2098	0	0	0
T92	1630	0	0	0
T93	0	10	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	15274	0	0
T1	22090	32	0	0
T2	3933	10	0	0
T3	5154	0	0	0
T4	51988	75	0	0
T5	4792	0	0	0
T6	29166	75	0	0
T7	1928	0	0	0
T8	4317	4	0	0
T9	5246	0	0	0
T10	1998	0	0	0
T11	0	5	0	0
T12	0	5	0	0
T21	0	29	0	0
T22	0	94	0	0
T23	0	14	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	1238	0	0
T12	6056	1	0	0
T21	22620	0	0	0
T22	113383	17	0	0
T23	5697	0	0	0
T24	5852	0	0	0
T53	0	17	0	0
T54	0	9	0	0
T60	6203	0	0	0
T61	8494	12	0	0
T62	0	13	0	0
T63	0	11	0	0
T85	5827	0	0	0
T86	0	18	0	0
T89	0	12	0	0
T90	0	1	0	0
T91	2098	0	0	0
T92	1630	0	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	15274	0	0
T1	22090	32	0	0
T2	3933	10	0	0
T3	5154	0	0	0
T4	51988	75	0	0
T5	4792	0	0	0
T6	29166	75	0	0
T7	1928	0	0	0
T8	4317	4	0	0
T9	5246	0	0	0
T10	1998	0	0	0
T11	0	5	0	0
T12	0	5	0	0
T21	0	29	0	0
T22	0	94	0	0
T23	0	14	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	1238	0	0
T12	6056	1	0	0
T21	22620	0	0	0
T22	113383	17	0	0
T23	5697	0	0	0
T24	5852	0	0	0
T53	0	17	0	0
T54	0	9	0	0
T60	6203	0	0	0
T61	8494	12	0	0
T62	0	13	0	0
T63	0	11	0	0
T85	5827	0	0	0
T86	0	18	0	0
T89	0	12	0	0
T90	0	1	0	0
T91	2098	0	0	0
T92	1630	0	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	15328	0	0
T1	22090	32	0	0
T2	3933	10	0	0
T3	5154	0	0	0
T4	51988	75	0	0
T5	4792	0	0	0
T6	29166	75	0	0
T7	1928	0	0	0
T8	4317	4	0	0
T9	5246	0	0	0
T10	1998	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	29	0	0
T22	0	93	0	0
T23	0	14	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	1280	0	0
T22	113383	14	0	0
T23	5697	0	0	0
T24	5852	0	0	0
T53	0	18	0	0
T54	0	11	0	0
T56	1434	0	0	0
T57	2112	0	0	0
T60	6203	0	0	0
T61	8494	14	0	0
T62	0	14	0	0
T63	0	14	0	0
T85	5827	0	0	0
T86	0	15	0	0
T89	0	12	0	0
T91	2098	0	0	0
T92	1630	0	0	0
T93	0	10	0	0
T94	0	17	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	15328	0	0
T1	22090	32	0	0
T2	3933	10	0	0
T3	5154	0	0	0
T4	51988	75	0	0
T5	4792	0	0	0
T6	29166	75	0	0
T7	1928	0	0	0
T8	4317	4	0	0
T9	5246	0	0	0
T10	1998	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T21	0	29	0	0
T22	0	93	0	0
T23	0	14	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	1280	0	0
T22	113383	14	0	0
T23	5697	0	0	0
T24	5852	0	0	0
T53	0	18	0	0
T54	0	11	0	0
T56	1434	0	0	0
T57	2112	0	0	0
T60	6203	0	0	0
T61	8494	14	0	0
T62	0	14	0	0
T63	0	14	0	0
T85	5827	0	0	0
T86	0	15	0	0
T89	0	12	0	0
T91	2098	0	0	0
T92	1630	0	0	0
T93	0	10	0	0
T94	0	17	0	0