Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_daon_por.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_sys.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_device.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c0.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c1.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_sys

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_sys_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_device

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_d0_usb_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	966869848	535138580	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	966869848	535138580	0	0
T1	1491416	565797	0	0
T2	265586	171767	0	0
T3	347962	62709	0	0
T4	3508984	2176794	0	0
T5	323502	52402	0	0
T6	1969130	648602	0	0
T7	130198	85535	0	0
T8	291446	214914	0	0
T9	354168	66050	0	0
T10	134920	90322	0	0

Line Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	59679324	36819049	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	36819049	0	0
T1	92058	45738	0	0
T2	16396	13694	0	0
T3	21481	4296	0	0
T4	216592	144338	0	0
T5	19971	3347	0	0
T6	121551	49470	0	0
T7	8039	5321	0	0
T8	17994	14000	0	0
T9	21864	4621	0	0
T10	8330	5617	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	57290300	35344716	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57290300	35344716	0	0
T1	88358	43902	0	0
T2	15740	13146	0	0
T3	20621	4124	0	0
T4	207934	138583	0	0
T5	19171	3213	0	0
T6	116693	47508	0	0
T7	7718	5108	0	0
T8	17269	13436	0	0
T9	20988	4436	0	0
T10	7997	5392	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	28646283	17668530	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646283	17668530	0	0
T1	44191	21949	0	0
T2	7870	6573	0	0
T3	10310	2061	0	0
T4	103987	69292	0	0
T5	9585	1606	0	0
T6	58345	23739	0	0
T7	3857	2553	0	0
T8	8637	6719	0	0
T9	10494	2217	0	0
T10	3998	2696	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	14322794	8831003	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	8831003	0	0
T1	22090	10963	0	0
T2	3933	3286	0	0
T3	5154	1029	0	0
T4	51988	34632	0	0
T5	4792	802	0	0
T6	29166	11848	0	0
T7	1928	1276	0	0
T8	4317	3359	0	0
T9	5246	1108	0	0
T10	1998	1347	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	28646144	17668404	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646144	17668404	0	0
T1	44181	21944	0	0
T2	7870	6573	0	0
T3	10310	2061	0	0
T4	103954	69281	0	0
T5	9586	1606	0	0
T6	58341	23703	0	0
T7	3857	2553	0	0
T8	8634	6717	0	0
T9	10495	2217	0	0
T10	3997	2696	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	59679324	32791712	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	32791712	0	0
T1	92058	33403	0	0
T2	16396	9974	0	0
T3	21481	4282	0	0
T4	216592	133763	0	0
T5	19971	3338	0	0
T6	121551	39601	0	0
T7	8039	5314	0	0
T8	17994	13212	0	0
T9	21864	4609	0	0
T10	8330	5610	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	59679324	32023740	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	32023740	0	0
T1	92058	31807	0	0
T2	16396	9826	0	0
T3	21481	3483	0	0
T4	216592	131328	0	0
T5	19971	3138	0	0
T6	121551	37127	0	0
T7	8039	5248	0	0
T8	17994	13045	0	0
T9	21864	3575	0	0
T10	8330	5543	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	59679324	32791463	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	32791463	0	0
T1	92058	33403	0	0
T2	16396	9974	0	0
T3	21481	4282	0	0
T4	216592	133763	0	0
T5	19971	3338	0	0
T6	121551	39542	0	0
T7	8039	5314	0	0
T8	17994	13212	0	0
T9	21864	4609	0	0
T10	8330	5610	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	59679324	32025572	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	32025572	0	0
T1	92058	31807	0	0
T2	16396	9826	0	0
T3	21481	3483	0	0
T4	216592	131328	0	0
T5	19971	3138	0	0
T6	121551	37177	0	0
T7	8039	5248	0	0
T8	17994	13045	0	0
T9	21864	3575	0	0
T10	8330	5543	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1808764	974183	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	974183	0	0
T1	2812	990	0	0
T2	490	289	0	0
T3	643	126	0	0
T4	6513	3909	0	0
T5	597	98	0	0
T6	3662	1085	0	0
T7	239	158	0	0
T8	538	390	0	0
T9	654	136	0	0
T10	248	167	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	57290300	31480287	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57290300	31480287	0	0
T1	88358	32066	0	0
T2	15740	9576	0	0
T3	20621	4110	0	0
T4	207934	128422	0	0
T5	19171	3204	0	0
T6	116693	38026	0	0
T7	7718	5102	0	0
T8	17269	12680	0	0
T9	20988	4424	0	0
T10	7997	5384	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	57290300	30741554	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57290300	30741554	0	0
T1	88358	30530	0	0
T2	15740	9432	0	0
T3	20621	3342	0	0
T4	207934	126050	0	0
T5	19171	3012	0	0
T6	116693	35698	0	0
T7	7718	5038	0	0
T8	17269	12520	0	0
T9	20988	3432	0	0
T10	7997	5320	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	28646283	15729076	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646283	15729076	0	0
T1	44191	16012	0	0
T2	7870	4783	0	0
T3	10310	2055	0	0
T4	103987	64147	0	0
T5	9585	1602	0	0
T6	58345	18931	0	0
T7	3857	2550	0	0
T8	8637	6339	0	0
T9	10494	2211	0	0
T10	3998	2692	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	28646283	15359721	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646283	15359721	0	0
T1	44191	15244	0	0
T2	7870	4711	0	0
T3	10310	1671	0	0
T4	103987	63013	0	0
T5	9585	1506	0	0
T6	58345	17777	0	0
T7	3857	2518	0	0
T8	8637	6259	0	0
T9	10494	1715	0	0
T10	3998	2660	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	14322794	7835351	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	7835351	0	0
T1	22090	7936	0	0
T2	3933	2375	0	0
T3	5154	1025	0	0
T4	51988	31952	0	0
T5	4792	798	0	0
T6	29166	9345	0	0
T7	1928	1274	0	0
T8	4317	3162	0	0
T9	5246	1104	0	0
T10	1998	1345	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	14322794	7650664	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	7650664	0	0
T1	22090	7552	0	0
T2	3933	2339	0	0
T3	5154	833	0	0
T4	51988	31370	0	0
T5	4792	750	0	0
T6	29166	8763	0	0
T7	1928	1258	0	0
T8	4317	3122	0	0
T9	5246	856	0	0
T10	1998	1329	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	14322794	7835351	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	7835351	0	0
T1	22090	7936	0	0
T2	3933	2375	0	0
T3	5154	1025	0	0
T4	51988	31952	0	0
T5	4792	798	0	0
T6	29166	9345	0	0
T7	1928	1274	0	0
T8	4317	3162	0	0
T9	5246	1104	0	0
T10	1998	1345	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	14322794	7650664	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	7650664	0	0
T1	22090	7552	0	0
T2	3933	2339	0	0
T3	5154	833	0	0
T4	51988	31370	0	0
T5	4792	750	0	0
T6	29166	8763	0	0
T7	1928	1258	0	0
T8	4317	3122	0	0
T9	5246	856	0	0
T10	1998	1329	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	28646144	15729212	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646144	15729212	0	0
T1	44181	16007	0	0
T2	7870	4783	0	0
T3	10310	2055	0	0
T4	103954	64131	0	0
T5	9586	1602	0	0
T6	58341	18957	0	0
T7	3857	2550	0	0
T8	8634	6337	0	0
T9	10495	2211	0	0
T10	3997	2692	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	28646144	15359701	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646144	15359701	0	0
T1	44181	15239	0	0
T2	7870	4711	0	0
T3	10310	1671	0	0
T4	103954	62977	0	0
T5	9586	1506	0	0
T6	58341	17767	0	0
T7	3857	2518	0	0
T8	8634	6257	0	0
T9	10495	1715	0	0
T10	3997	2660	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	59679324	31699417	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59679324	31699417	0	0
T1	92058	31075	0	0
T2	16396	9559	0	0
T3	21481	3483	0	0
T4	216592	129657	0	0
T5	19971	3138	0	0
T6	121551	35282	0	0
T7	8039	5248	0	0
T8	17994	12936	0	0
T9	21864	3575	0	0
T10	8330	5543	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	14322794	7757491	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	7757491	0	0
T1	22090	7761	0	0
T2	3933	2311	0	0
T3	5154	1025	0	0
T4	51988	31550	0	0
T5	4792	798	0	0
T6	29166	8887	0	0
T7	1928	1274	0	0
T8	4317	3136	0	0
T9	5246	1104	0	0
T10	1998	1345	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	14322794	7490550	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	7490550	0	0
T1	22090	7552	0	0
T2	3933	2336	0	0
T3	5154	833	0	0
T4	51988	31370	0	0
T5	4792	750	0	0
T6	29166	8763	0	0
T7	1928	1258	0	0
T8	4317	3122	0	0
T9	5246	856	0	0
T10	1998	1329	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	57290300	30117017	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57290300	30117017	0	0
T1	88358	30530	0	0
T2	15740	9432	0	0
T3	20621	3342	0	0
T4	207934	126042	0	0
T5	19171	3012	0	0
T6	116693	35646	0	0
T7	7718	5038	0	0
T8	17269	12520	0	0
T9	20988	3432	0	0
T10	7997	5320	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	28646283	15035536	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646283	15035536	0	0
T1	44191	15244	0	0
T2	7870	4711	0	0
T3	10310	1671	0	0
T4	103987	63013	0	0
T5	9585	1506	0	0
T6	58345	17801	0	0
T7	3857	2518	0	0
T8	8637	6259	0	0
T9	10494	1715	0	0
T10	3998	2660	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	28646144	15050161	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28646144	15050161	0	0
T1	44181	15239	0	0
T2	7870	4711	0	0
T3	10310	1671	0	0
T4	103954	63001	0	0
T5	9586	1506	0	0
T6	58341	17793	0	0
T7	3857	2518	0	0
T8	8634	6257	0	0
T9	10495	1715	0	0
T10	3997	2660	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1808764	931428	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	931428	0	0
T1	2812	944	0	0
T2	490	285	0	0
T3	643	102	0	0
T4	6513	3836	0	0
T5	597	92	0	0
T6	3662	1013	0	0
T7	239	156	0	0
T8	538	385	0	0
T9	654	105	0	0
T10	248	165	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	14322794	7504068	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	7504068	0	0
T1	22090	7552	0	0
T2	3933	2339	0	0
T3	5154	833	0	0
T4	51988	31358	0	0
T5	4792	750	0	0
T6	29166	8763	0	0
T7	1928	1258	0	0
T8	4317	3122	0	0
T9	5246	856	0	0
T10	1998	1329	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	14322794	7499516	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	7499516	0	0
T1	22090	7552	0	0
T2	3933	2339	0	0
T3	5154	833	0	0
T4	51988	31370	0	0
T5	4792	750	0	0
T6	29166	8763	0	0
T7	1928	1258	0	0
T8	4317	3122	0	0
T9	5246	856	0	0
T10	1998	1329	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	14322794	7511562	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14322794	7511562	0	0
T1	22090	7552	0	0
T2	3933	2339	0	0
T3	5154	833	0	0
T4	51988	31354	0	0
T5	4792	750	0	0
T6	29166	8763	0	0
T7	1928	1258	0	0
T8	4317	3122	0	0
T9	5246	856	0	0
T10	1998	1329	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1808764	1125724	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	1125724	0	0
T1	2812	1428	0	0
T2	490	411	0	0
T3	643	130	0	0
T4	6513	4348	0	0
T5	597	102	0	0
T6	3662	1505	0	0
T7	239	160	0	0
T8	538	421	0	0
T9	654	140	0	0
T10	248	169	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1808764	1106157	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808764	1106157	0	0
T1	2812	1388	0	0
T2	490	409	0	0
T3	643	106	0	0
T4	6513	4294	0	0
T5	597	96	0	0
T6	3662	1451	0	0
T7	239	158	0	0
T8	538	417	0	0
T9	654	109	0	0
T10	248	167	0	0