Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13474733	7947	0	0
alert_regwen_rd_A	13474733	6270	0	0
cpu_regwen_rd_A	13474733	6131	0	0
sw_rst_ctrl_n_0_rd_A	13474733	11314	0	0
sw_rst_ctrl_n_1_rd_A	13474733	11232	0	0
sw_rst_ctrl_n_2_rd_A	13474733	10990	0	0
sw_rst_ctrl_n_3_rd_A	13474733	11375	0	0
sw_rst_ctrl_n_4_rd_A	13474733	11241	0	0
sw_rst_ctrl_n_5_rd_A	13474733	11059	0	0
sw_rst_ctrl_n_6_rd_A	13474733	11271	0	0
sw_rst_ctrl_n_7_rd_A	13474733	11303	0	0
sw_rst_regwen_0_rd_A	13474733	6394	0	0
sw_rst_regwen_1_rd_A	13474733	6619	0	0
sw_rst_regwen_2_rd_A	13474733	6601	0	0
sw_rst_regwen_3_rd_A	13474733	6457	0	0
sw_rst_regwen_4_rd_A	13474733	6585	0	0
sw_rst_regwen_5_rd_A	13474733	6656	0	0
sw_rst_regwen_6_rd_A	13474733	6593	0	0
sw_rst_regwen_7_rd_A	13474733	6622	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	7947	0	0
T64	10749	1	0	0
T67	2846	10	0	0
T68	6295	357	0	0
T69	3324	460	0	0
T73	2617	5	0	0
T95	4416	21	0	0
T96	2935	254	0	0
T97	8517	537	0	0
T99	7154	255	0	0
T100	21056	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	6270	0	0
T22	103105	83	0	0
T23	4692	0	0	0
T24	5499	0	0	0
T56	1344	0	0	0
T57	1911	0	0	0
T60	5912	0	0	0
T61	8452	0	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T104	0	42	0	0
T105	0	82	0	0
T106	0	65	0	0
T107	0	131	0	0
T108	0	269	0	0
T109	0	591	0	0
T110	0	402	0	0
T111	0	58	0	0
T135	0	56	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	6131	0	0
T22	103105	116	0	0
T23	4692	0	0	0
T24	5499	0	0	0
T56	1344	0	0	0
T57	1911	0	0	0
T60	5912	0	0	0
T61	8452	0	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T104	0	62	0	0
T105	0	83	0	0
T106	0	97	0	0
T107	0	128	0	0
T108	0	208	0	0
T109	0	542	0	0
T110	0	374	0	0
T111	0	55	0	0
T135	0	30	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	11314	0	0
T11	2377	11	0	0
T12	5859	10	0	0
T20	1831	0	0	0
T21	17415	0	0	0
T22	103105	333	0	0
T23	4692	43	0	0
T24	5499	0	0	0
T49	0	31	0	0
T54	0	164	0	0
T57	0	15	0	0
T60	0	9	0	0
T63	0	213	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T136	0	43	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	11232	0	0
T11	2377	1	0	0
T12	5859	12	0	0
T20	1831	0	0	0
T21	17415	0	0	0
T22	103105	320	0	0
T23	4692	55	0	0
T24	5499	0	0	0
T49	0	58	0	0
T54	0	156	0	0
T57	0	6	0	0
T60	0	13	0	0
T63	0	196	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T136	0	34	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	10990	0	0
T11	2377	20	0	0
T12	5859	7	0	0
T20	1831	0	0	0
T21	17415	0	0	0
T22	103105	297	0	0
T23	4692	63	0	0
T24	5499	0	0	0
T49	0	32	0	0
T54	0	143	0	0
T57	0	9	0	0
T60	0	10	0	0
T63	0	200	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T136	0	16	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	11375	0	0
T11	2377	8	0	0
T12	5859	10	0	0
T20	1831	0	0	0
T21	17415	0	0	0
T22	103105	335	0	0
T23	4692	60	0	0
T24	5499	0	0	0
T49	0	44	0	0
T54	0	152	0	0
T57	0	7	0	0
T60	0	13	0	0
T63	0	202	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T136	0	42	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	11241	0	0
T11	2377	5	0	0
T12	5859	18	0	0
T20	1831	0	0	0
T21	17415	0	0	0
T22	103105	316	0	0
T23	4692	54	0	0
T24	5499	0	0	0
T49	0	51	0	0
T54	0	154	0	0
T57	0	4	0	0
T60	0	16	0	0
T63	0	213	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T136	0	26	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	11059	0	0
T11	2377	23	0	0
T12	5859	16	0	0
T20	1831	0	0	0
T21	17415	0	0	0
T22	103105	339	0	0
T23	4692	53	0	0
T24	5499	0	0	0
T49	0	40	0	0
T54	0	164	0	0
T57	0	9	0	0
T60	0	11	0	0
T63	0	169	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T136	0	22	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	11271	0	0
T11	2377	6	0	0
T12	5859	6	0	0
T20	1831	0	0	0
T21	17415	0	0	0
T22	103105	338	0	0
T23	4692	48	0	0
T24	5499	0	0	0
T49	0	52	0	0
T54	0	132	0	0
T57	0	14	0	0
T60	0	14	0	0
T63	0	218	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T136	0	34	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	11303	0	0
T11	2377	5	0	0
T12	5859	16	0	0
T20	1831	0	0	0
T21	17415	0	0	0
T22	103105	309	0	0
T23	4692	47	0	0
T24	5499	0	0	0
T49	0	49	0	0
T54	0	171	0	0
T60	0	30	0	0
T63	0	209	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T93	0	113	0	0
T136	0	62	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	6394	0	0
T12	5859	10	0	0
T21	17415	0	0	0
T22	103105	137	0	0
T23	4692	0	0	0
T24	5499	0	0	0
T36	0	39	0	0
T40	0	9	0	0
T54	0	37	0	0
T60	5912	11	0	0
T61	8452	0	0	0
T63	0	38	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T93	0	30	0	0
T104	0	44	0	0
T105	0	66	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	6619	0	0
T12	5859	7	0	0
T21	17415	0	0	0
T22	103105	140	0	0
T23	4692	0	0	0
T24	5499	0	0	0
T36	0	32	0	0
T54	0	30	0	0
T60	5912	12	0	0
T61	8452	0	0	0
T63	0	27	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T93	0	8	0	0
T104	0	49	0	0
T105	0	66	0	0
T137	0	8	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	6601	0	0
T12	5859	4	0	0
T21	17415	0	0	0
T22	103105	93	0	0
T23	4692	0	0	0
T24	5499	0	0	0
T36	0	38	0	0
T40	0	9	0	0
T54	0	33	0	0
T60	5912	19	0	0
T61	8452	0	0	0
T63	0	39	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T93	0	10	0	0
T104	0	51	0	0
T105	0	51	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	6457	0	0
T12	5859	14	0	0
T21	17415	0	0	0
T22	103105	120	0	0
T23	4692	0	0	0
T24	5499	0	0	0
T36	0	24	0	0
T40	0	4	0	0
T54	0	39	0	0
T60	5912	14	0	0
T61	8452	0	0	0
T63	0	15	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T93	0	30	0	0
T104	0	45	0	0
T105	0	42	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	6585	0	0
T12	5859	1	0	0
T21	17415	0	0	0
T22	103105	128	0	0
T23	4692	0	0	0
T24	5499	0	0	0
T36	0	38	0	0
T40	0	6	0	0
T54	0	30	0	0
T60	5912	5	0	0
T61	8452	0	0	0
T63	0	37	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T93	0	28	0	0
T104	0	50	0	0
T105	0	62	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	6656	0	0
T12	5859	10	0	0
T21	17415	0	0	0
T22	103105	107	0	0
T23	4692	0	0	0
T24	5499	0	0	0
T36	0	26	0	0
T40	0	7	0	0
T54	0	31	0	0
T60	5912	2	0	0
T61	8452	0	0	0
T63	0	39	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T93	0	24	0	0
T104	0	47	0	0
T105	0	49	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	6593	0	0
T12	5859	11	0	0
T21	17415	0	0	0
T22	103105	104	0	0
T23	4692	0	0	0
T24	5499	0	0	0
T36	0	25	0	0
T40	0	9	0	0
T54	0	36	0	0
T60	5912	8	0	0
T61	8452	0	0	0
T63	0	25	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T93	0	12	0	0
T104	0	44	0	0
T105	0	52	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13474733	6622	0	0
T12	5859	6	0	0
T21	17415	0	0	0
T22	103105	120	0	0
T23	4692	0	0	0
T24	5499	0	0	0
T36	0	32	0	0
T40	0	9	0	0
T54	0	39	0	0
T60	5912	4	0	0
T61	8452	0	0	0
T63	0	36	0	0
T85	5285	0	0	0
T91	2032	0	0	0
T92	1611	0	0	0
T93	0	23	0	0
T104	0	50	0	0
T105	0	50	0	0