Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	645236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

386242

1

T1

5

T2

1035

T4

1180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	550062	1			T2	1543		T3	1		T4	1755
values[0x0]	240787	1			T1	5		T2	561		T4	709
values[0x1]	240629	1			T1	7		T2	594		T4	672

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	541858	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

489620

1

T1

6

T2

1306

T4

1485

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3570	1			T2	8		T4	12		T6	100
valid_sources[0x01]	3485	1			T2	17		T4	13		T6	85
valid_sources[0x02]	3326	1			T2	9		T4	13		T5	14
valid_sources[0x03]	3231	1			T2	5		T4	6		T5	18
valid_sources[0x04]	4521	1			T2	15		T4	11		T5	3
valid_sources[0x05]	3452	1			T1	1		T2	6		T4	14
valid_sources[0x06]	5025	1			T2	6		T4	15		T5	14
valid_sources[0x07]	3767	1			T2	5		T4	12		T5	5
valid_sources[0x08]	3202	1			T2	9		T4	12		T5	3
valid_sources[0x09]	3721	1			T2	14		T4	7		T5	11
valid_sources[0x0a]	3155	1			T2	8		T4	2		T5	1
valid_sources[0x0b]	3145	1			T2	9		T4	14		T5	11
valid_sources[0x0c]	6791	1			T2	8		T4	10		T5	11
valid_sources[0x0d]	6699	1			T2	13		T4	10		T5	15
valid_sources[0x0e]	3935	1			T2	4		T4	17		T5	3
valid_sources[0x0f]	3452	1			T2	9		T4	17		T5	6
valid_sources[0x10]	3383	1			T2	10		T4	15		T5	7
valid_sources[0x11]	3268	1			T2	4		T4	12		T5	18
valid_sources[0x12]	3782	1			T2	12		T4	11		T5	10
valid_sources[0x13]	4431	1			T2	10		T4	12		T5	10
valid_sources[0x14]	4341	1			T2	3		T4	12		T5	56
valid_sources[0x15]	3461	1			T1	3		T2	5		T4	14
valid_sources[0x16]	3941	1			T2	10		T4	13		T5	5
valid_sources[0x17]	3946	1			T2	10		T4	23		T5	27
valid_sources[0x18]	3746	1			T2	4		T4	16		T5	22
valid_sources[0x19]	3709	1			T2	3		T4	12		T5	7
valid_sources[0x1a]	3662	1			T2	17		T4	8		T5	6
valid_sources[0x1b]	3940	1			T2	14		T4	8		T5	16
valid_sources[0x1c]	3873	1			T2	9		T4	14		T5	36
valid_sources[0x1d]	3903	1			T2	4		T4	12		T5	20
valid_sources[0x1e]	6511	1			T2	12		T4	11		T5	5
valid_sources[0x1f]	3825	1			T2	12		T4	10		T5	29
valid_sources[0x20]	3117	1			T2	8		T4	15		T5	13
valid_sources[0x21]	4122	1			T2	12		T4	11		T5	6
valid_sources[0x22]	3304	1			T2	5		T4	9		T5	12
valid_sources[0x23]	3115	1			T2	8		T4	14		T5	20
valid_sources[0x24]	4255	1			T2	19		T4	11		T5	16
valid_sources[0x25]	4024	1			T2	12		T4	10		T5	3
valid_sources[0x26]	3826	1			T2	12		T4	15		T5	29
valid_sources[0x27]	3378	1			T2	11		T4	11		T5	5
valid_sources[0x28]	3820	1			T2	8		T4	13		T5	20
valid_sources[0x29]	3827	1			T2	3		T4	13		T5	16
valid_sources[0x2a]	4040	1			T2	14		T4	13		T5	4
valid_sources[0x2b]	4820	1			T2	17		T4	7		T5	5
valid_sources[0x2c]	4092	1			T2	19		T4	10		T5	10
valid_sources[0x2d]	3612	1			T2	14		T4	15		T5	25
valid_sources[0x2e]	3144	1			T2	5		T4	13		T5	16
valid_sources[0x2f]	3758	1			T2	7		T4	13		T5	12
valid_sources[0x30]	7275	1			T2	12		T4	8		T5	15
valid_sources[0x31]	4221	1			T2	16		T4	10		T5	36
valid_sources[0x32]	3473	1			T2	8		T4	11		T5	29
valid_sources[0x33]	3455	1			T2	1		T4	7		T6	91
valid_sources[0x34]	3845	1			T2	11		T4	8		T5	27
valid_sources[0x35]	3163	1			T2	15		T4	10		T5	8
valid_sources[0x36]	4440	1			T2	14		T4	12		T5	2
valid_sources[0x37]	4179	1			T2	10		T4	14		T5	6
valid_sources[0x38]	3858	1			T2	23		T4	14		T5	10
valid_sources[0x39]	3546	1			T2	6		T4	7		T5	7
valid_sources[0x3a]	3207	1			T2	21		T4	9		T5	7
valid_sources[0x3b]	3658	1			T2	20		T4	8		T5	29
valid_sources[0x3c]	3499	1			T2	17		T4	10		T5	4
valid_sources[0x3d]	4345	1			T2	15		T4	15		T5	27
valid_sources[0x3e]	3786	1			T2	8		T4	11		T5	23
valid_sources[0x3f]	3781	1			T2	10		T4	13		T5	51
valid_sources[0x40]	3884	1			T2	12		T4	11		T5	29
valid_sources[0x41]	3626	1			T2	12		T4	14		T5	2
valid_sources[0x42]	4719	1			T2	9		T4	11		T5	3
valid_sources[0x43]	4135	1			T2	9		T4	8		T5	11
valid_sources[0x44]	3953	1			T2	3		T4	6		T5	10
valid_sources[0x45]	4653	1			T2	7		T4	13		T5	2
valid_sources[0x46]	3255	1			T2	8		T4	14		T5	11
valid_sources[0x47]	3260	1			T2	15		T4	20		T5	16
valid_sources[0x48]	3489	1			T2	12		T4	17		T5	44
valid_sources[0x49]	3243	1			T2	11		T4	22		T5	11
valid_sources[0x4a]	3430	1			T2	15		T4	14		T5	3
valid_sources[0x4b]	3374	1			T2	10		T4	13		T5	11
valid_sources[0x4c]	3378	1			T2	11		T4	15		T6	63
valid_sources[0x4d]	3863	1			T2	20		T4	13		T5	17
valid_sources[0x4e]	4032	1			T2	12		T4	8		T6	128
valid_sources[0x4f]	4877	1			T2	24		T4	8		T5	12
valid_sources[0x50]	5262	1			T2	7		T4	15		T5	35
valid_sources[0x51]	4212	1			T2	4		T4	14		T5	27
valid_sources[0x52]	3653	1			T2	14		T4	13		T5	14
valid_sources[0x53]	3830	1			T2	18		T4	15		T5	6
valid_sources[0x54]	3769	1			T2	16		T4	11		T6	90
valid_sources[0x55]	4335	1			T2	18		T4	11		T5	14
valid_sources[0x56]	6469	1			T2	10		T4	12		T5	11
valid_sources[0x57]	4163	1			T2	13		T4	10		T5	17
valid_sources[0x58]	3736	1			T2	7		T4	16		T5	11
valid_sources[0x59]	5101	1			T2	12		T4	22		T5	2
valid_sources[0x5a]	4442	1			T2	10		T4	16		T6	109
valid_sources[0x5b]	3991	1			T2	5		T4	14		T6	103
valid_sources[0x5c]	3725	1			T2	8		T4	7		T5	8
valid_sources[0x5d]	5012	1			T2	9		T4	16		T5	42
valid_sources[0x5e]	3426	1			T2	3		T4	15		T5	13
valid_sources[0x5f]	3410	1			T2	15		T4	8		T5	15
valid_sources[0x60]	7328	1			T2	15		T4	10		T5	3
valid_sources[0x61]	3698	1			T2	11		T4	10		T5	14
valid_sources[0x62]	3930	1			T2	10		T4	8		T5	3
valid_sources[0x63]	3422	1			T2	18		T4	12		T5	12
valid_sources[0x64]	3733	1			T2	6		T4	13		T5	4
valid_sources[0x65]	3973	1			T2	8		T4	6		T5	28
valid_sources[0x66]	3454	1			T2	9		T4	10		T5	11
valid_sources[0x67]	4456	1			T2	11		T4	10		T5	11
valid_sources[0x68]	3607	1			T2	8		T4	12		T5	30
valid_sources[0x69]	3495	1			T2	17		T4	9		T5	16
valid_sources[0x6a]	3531	1			T1	1		T2	19		T4	6
valid_sources[0x6b]	4212	1			T2	13		T4	12		T5	8
valid_sources[0x6c]	4459	1			T2	8		T4	15		T5	17
valid_sources[0x6d]	4156	1			T2	7		T4	9		T5	6
valid_sources[0x6e]	3829	1			T2	9		T3	1		T4	12
valid_sources[0x6f]	3568	1			T2	15		T4	3		T5	19
valid_sources[0x70]	3610	1			T1	4		T2	7		T4	12
valid_sources[0x71]	3178	1			T2	16		T4	21		T5	16
valid_sources[0x72]	3313	1			T2	9		T4	17		T5	6
valid_sources[0x73]	6939	1			T2	6		T4	14		T5	16
valid_sources[0x74]	3456	1			T2	8		T4	9		T5	4
valid_sources[0x75]	4530	1			T2	3		T4	8		T5	9
valid_sources[0x76]	3598	1			T1	1		T2	11		T4	8
valid_sources[0x77]	3918	1			T2	7		T4	16		T5	4
valid_sources[0x78]	3511	1			T2	3		T4	21		T5	13
valid_sources[0x79]	3458	1			T2	20		T4	8		T5	8
valid_sources[0x7a]	4943	1			T2	5		T4	16		T5	24
valid_sources[0x7b]	7765	1			T2	5		T4	9		T5	7
valid_sources[0x7c]	3446	1			T2	11		T4	18		T5	7
valid_sources[0x7d]	7069	1			T2	14		T4	14		T6	65
valid_sources[0x7e]	5653	1			T2	28		T4	9		T5	8
valid_sources[0x7f]	4131	1			T2	8		T4	13		T5	4
valid_sources[0x80]	4084	1			T2	12		T4	19		T5	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

257831

1

T2

739

T4

833

T5

694

values[0x0]

all_enables

biggest_size

83712

1

T1

3

T2

182

T4

250

values[0x1]

all_enables

biggest_size

44699

1

T1

2

T2

114

T4

97