Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T6
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T6

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	57928280	9430	0	0
CascadeEffAonToRstPorAboveRise_A	57928280	9430	0	0
CascadeEffAonToRstPorIoAboveFall_A	55609468	9430	0	0
CascadeEffAonToRstPorIoAboveRise_A	55609468	9430	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27805487	9430	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27805487	9430	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13902597	9430	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13902597	9430	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27805480	9430	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27805480	9430	0	0
CascadeLcToLcAboveFall_A	57928280	23108	0	0
CascadeLcToLcAboveRise_A	57928280	23108	0	0
CascadeLcToLcAonAboveFall_A	1755818	23108	0	0
CascadeLcToLcAonAboveRise_A	1755818	23108	0	0
CascadeLcToLcShadowedAboveFall_A	57928280	23108	0	0
CascadeLcToLcShadowedAboveRise_A	57928280	23108	0	0
CascadePorToAonAboveFall_A	1755818	7592	0	0
CascadeSysToSysAboveFall_A	57928280	23108	0	0
CascadeSysToSysAboveRise_A	57928280	23108	0	0
ScanRstToAonRise_A	1755818	236	0	0
StablePorToAonRise_A	1755818	9430	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12324861	23108	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12324861	23108	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12324861	23108	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12324861	23108	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13902597	23108	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13902597	23108	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12324861	23108	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12324861	23108	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12324861	23108	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12324861	23108	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57928280	9430	0	0
T1	6815	1	0	0
T2	145171	20	0	0
T3	19343	2	0	0
T4	97842	21	0	0
T5	123068	27	0	0
T6	157879	179	0	0
T7	61511	5	0	0
T8	6596	1	0	0
T9	121429	27	0	0
T10	15506	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57928280	9430	0	0
T1	6815	1	0	0
T2	145171	20	0	0
T3	19343	2	0	0
T4	97842	21	0	0
T5	123068	27	0	0
T6	157879	179	0	0
T7	61511	5	0	0
T8	6596	1	0	0
T9	121429	27	0	0
T10	15506	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55609468	9430	0	0
T1	6543	1	0	0
T2	139376	20	0	0
T3	18569	2	0	0
T4	93927	21	0	0
T5	118182	27	0	0
T6	151557	179	0	0
T7	59039	5	0	0
T8	6333	1	0	0
T9	116567	27	0	0
T10	14885	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55609468	9430	0	0
T1	6543	1	0	0
T2	139376	20	0	0
T3	18569	2	0	0
T4	93927	21	0	0
T5	118182	27	0	0
T6	151557	179	0	0
T7	59039	5	0	0
T8	6333	1	0	0
T9	116567	27	0	0
T10	14885	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805487	9430	0	0
T1	3271	1	0	0
T2	69689	20	0	0
T3	9284	2	0	0
T4	46964	21	0	0
T5	59082	27	0	0
T6	757834	179	0	0
T7	29523	5	0	0
T8	3165	1	0	0
T9	58265	27	0	0
T10	7443	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805487	9430	0	0
T1	3271	1	0	0
T2	69689	20	0	0
T3	9284	2	0	0
T4	46964	21	0	0
T5	59082	27	0	0
T6	757834	179	0	0
T7	29523	5	0	0
T8	3165	1	0	0
T9	58265	27	0	0
T10	7443	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	9430	0	0
T1	1635	1	0	0
T2	34844	20	0	0
T3	4640	2	0	0
T4	23481	21	0	0
T5	29537	27	0	0
T6	378922	179	0	0
T7	14761	5	0	0
T8	1582	1	0	0
T9	29140	27	0	0
T10	3719	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	9430	0	0
T1	1635	1	0	0
T2	34844	20	0	0
T3	4640	2	0	0
T4	23481	21	0	0
T5	29537	27	0	0
T6	378922	179	0	0
T7	14761	5	0	0
T8	1582	1	0	0
T9	29140	27	0	0
T10	3719	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805480	9430	0	0
T1	3272	1	0	0
T2	69687	20	0	0
T3	9284	2	0	0
T4	46969	21	0	0
T5	59076	27	0	0
T6	757811	179	0	0
T7	29523	5	0	0
T8	3165	1	0	0
T9	58270	27	0	0
T10	7442	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805480	9430	0	0
T1	3272	1	0	0
T2	69687	20	0	0
T3	9284	2	0	0
T4	46969	21	0	0
T5	59076	27	0	0
T6	757811	179	0	0
T7	29523	5	0	0
T8	3165	1	0	0
T9	58270	27	0	0
T10	7442	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57928280	23108	0	0
T1	6815	1	0	0
T2	145171	52	0	0
T3	19343	2	0	0
T4	97842	62	0	0
T5	123068	102	0	0
T6	157879	502	0	0
T7	61511	13	0	0
T8	6596	2	0	0
T9	121429	102	0	0
T10	15506	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57928280	23108	0	0
T1	6815	1	0	0
T2	145171	52	0	0
T3	19343	2	0	0
T4	97842	62	0	0
T5	123068	102	0	0
T6	157879	502	0	0
T7	61511	13	0	0
T8	6596	2	0	0
T9	121429	102	0	0
T10	15506	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1755818	23108	0	0
T1	204	1	0	0
T2	4412	52	0	0
T3	580	2	0	0
T4	3036	62	0	0
T5	3707	102	0	0
T6	48080	502	0	0
T7	1844	13	0	0
T8	197	2	0	0
T9	3658	102	0	0
T10	463	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1755818	23108	0	0
T1	204	1	0	0
T2	4412	52	0	0
T3	580	2	0	0
T4	3036	62	0	0
T5	3707	102	0	0
T6	48080	502	0	0
T7	1844	13	0	0
T8	197	2	0	0
T9	3658	102	0	0
T10	463	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57928280	23108	0	0
T1	6815	1	0	0
T2	145171	52	0	0
T3	19343	2	0	0
T4	97842	62	0	0
T5	123068	102	0	0
T6	157879	502	0	0
T7	61511	13	0	0
T8	6596	2	0	0
T9	121429	102	0	0
T10	15506	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57928280	23108	0	0
T1	6815	1	0	0
T2	145171	52	0	0
T3	19343	2	0	0
T4	97842	62	0	0
T5	123068	102	0	0
T6	157879	502	0	0
T7	61511	13	0	0
T8	6596	2	0	0
T9	121429	102	0	0
T10	15506	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1755818	7592	0	0
T1	204	1	0	0
T2	4412	12	0	0
T3	580	20	0	0
T4	3036	10	0	0
T5	3707	27	0	0
T6	48080	76	0	0
T7	1844	3	0	0
T8	197	1	0	0
T9	3658	27	0	0
T10	463	14	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57928280	23108	0	0
T1	6815	1	0	0
T2	145171	52	0	0
T3	19343	2	0	0
T4	97842	62	0	0
T5	123068	102	0	0
T6	157879	502	0	0
T7	61511	13	0	0
T8	6596	2	0	0
T9	121429	102	0	0
T10	15506	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57928280	23108	0	0
T1	6815	1	0	0
T2	145171	52	0	0
T3	19343	2	0	0
T4	97842	62	0	0
T5	123068	102	0	0
T6	157879	502	0	0
T7	61511	13	0	0
T8	6596	2	0	0
T9	121429	102	0	0
T10	15506	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1755818	236	0	0
T2	4412	2	0	0
T3	580	0	0	0
T4	3036	1	0	0
T5	3707	0	0	0
T6	48080	8	0	0
T7	1844	0	0	0
T8	197	0	0	0
T9	3658	0	0	0
T10	463	0	0	0
T11	3689	0	0	0
T21	0	17	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	4	0	0
T75	0	3	0	0
T90	0	1	0	0
T91	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1755818	9430	0	0
T1	204	1	0	0
T2	4412	20	0	0
T3	580	2	0	0
T4	3036	21	0	0
T5	3707	27	0	0
T6	48080	179	0	0
T7	1844	5	0	0
T8	197	1	0	0
T9	3658	27	0	0
T10	463	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12324861	23108	0	0
T1	1616	1	0	0
T2	29912	52	0	0
T3	4599	2	0	0
T4	18475	62	0	0
T5	26160	102	0	0
T6	334035	502	0	0
T7	14159	13	0	0
T8	1439	2	0	0
T9	25966	102	0	0
T10	3558	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12324861	23108	0	0
T1	1616	1	0	0
T2	29912	52	0	0
T3	4599	2	0	0
T4	18475	62	0	0
T5	26160	102	0	0
T6	334035	502	0	0
T7	14159	13	0	0
T8	1439	2	0	0
T9	25966	102	0	0
T10	3558	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12324861	23108	0	0
T1	1616	1	0	0
T2	29912	52	0	0
T3	4599	2	0	0
T4	18475	62	0	0
T5	26160	102	0	0
T6	334035	502	0	0
T7	14159	13	0	0
T8	1439	2	0	0
T9	25966	102	0	0
T10	3558	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12324861	23108	0	0
T1	1616	1	0	0
T2	29912	52	0	0
T3	4599	2	0	0
T4	18475	62	0	0
T5	26160	102	0	0
T6	334035	502	0	0
T7	14159	13	0	0
T8	1439	2	0	0
T9	25966	102	0	0
T10	3558	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	23108	0	0
T1	1635	1	0	0
T2	34844	52	0	0
T3	4640	2	0	0
T4	23481	62	0	0
T5	29537	102	0	0
T6	378922	502	0	0
T7	14761	13	0	0
T8	1582	2	0	0
T9	29140	102	0	0
T10	3719	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	23108	0	0
T1	1635	1	0	0
T2	34844	52	0	0
T3	4640	2	0	0
T4	23481	62	0	0
T5	29537	102	0	0
T6	378922	502	0	0
T7	14761	13	0	0
T8	1582	2	0	0
T9	29140	102	0	0
T10	3719	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12324861	23108	0	0
T1	1616	1	0	0
T2	29912	52	0	0
T3	4599	2	0	0
T4	18475	62	0	0
T5	26160	102	0	0
T6	334035	502	0	0
T7	14159	13	0	0
T8	1439	2	0	0
T9	25966	102	0	0
T10	3558	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12324861	23108	0	0
T1	1616	1	0	0
T2	29912	52	0	0
T3	4599	2	0	0
T4	18475	62	0	0
T5	26160	102	0	0
T6	334035	502	0	0
T7	14159	13	0	0
T8	1439	2	0	0
T9	25966	102	0	0
T10	3558	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12324861	23108	0	0
T1	1616	1	0	0
T2	29912	52	0	0
T3	4599	2	0	0
T4	18475	62	0	0
T5	26160	102	0	0
T6	334035	502	0	0
T7	14159	13	0	0
T8	1439	2	0	0
T9	25966	102	0	0
T10	3558	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12324861	23108	0	0
T1	1616	1	0	0
T2	29912	52	0	0
T3	4599	2	0	0
T4	18475	62	0	0
T5	26160	102	0	0
T6	334035	502	0	0
T7	14159	13	0	0
T8	1439	2	0	0
T9	25966	102	0	0
T10	3558	2	0	0