Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T21
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T20
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T21
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T20
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T21
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T20
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T20
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13902597	14611	0	0
gen_assertions[0].RstEnOn_A	13902597	1094	0	0
gen_assertions[0].RstNOff_A	13902597	14611	0	0
gen_assertions[0].RstNOn_A	13902597	1094	0	0
gen_assertions[1].RstEnOff_A	55609468	13239	0	0
gen_assertions[1].RstEnOn_A	55609468	1083	0	0
gen_assertions[1].RstNOff_A	55609468	13239	0	0
gen_assertions[1].RstNOn_A	55609468	1083	0	0
gen_assertions[2].RstEnOff_A	27805487	13301	0	0
gen_assertions[2].RstEnOn_A	27805487	1106	0	0
gen_assertions[2].RstNOff_A	27805487	13301	0	0
gen_assertions[2].RstNOn_A	27805487	1106	0	0
gen_assertions[3].RstEnOff_A	27805480	13335	0	0
gen_assertions[3].RstEnOn_A	27805480	1124	0	0
gen_assertions[3].RstNOff_A	27805480	13335	0	0
gen_assertions[3].RstNOn_A	27805480	1124	0	0
gen_assertions[4].RstEnOff_A	1755818	22989	0	0
gen_assertions[4].RstEnOn_A	1755818	1205	0	0
gen_assertions[4].RstNOff_A	1755818	22989	0	0
gen_assertions[4].RstNOn_A	1755818	1205	0	0
gen_assertions[5].RstEnOff_A	13902597	14873	0	0
gen_assertions[5].RstEnOn_A	13902597	1234	0	0
gen_assertions[5].RstNOff_A	13902597	14873	0	0
gen_assertions[5].RstNOn_A	13902597	1234	0	0
gen_assertions[6].RstEnOff_A	13902597	14940	0	0
gen_assertions[6].RstEnOn_A	13902597	1298	0	0
gen_assertions[6].RstNOff_A	13902597	14940	0	0
gen_assertions[6].RstNOn_A	13902597	1298	0	0
gen_assertions[7].RstEnOff_A	13902597	14961	0	0
gen_assertions[7].RstEnOn_A	13902597	1326	0	0
gen_assertions[7].RstNOff_A	13902597	14961	0	0
gen_assertions[7].RstNOn_A	13902597	1326	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	14611	0	0
T2	34844	32	0	0
T3	4640	0	0	0
T4	23481	41	0	0
T5	29537	75	0	0
T6	378922	340	0	0
T7	14761	15	0	0
T8	1582	1	0	0
T9	29140	75	0	0
T10	3719	0	0	0
T11	29402	75	0	0
T20	0	4	0	0
T21	0	419	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	1094	0	0
T6	378922	18	0	0
T7	14761	9	0	0
T8	1582	0	0	0
T9	29140	0	0	0
T10	3719	0	0	0
T11	29402	0	0	0
T20	2830	0	0	0
T21	244632	7	0	0
T22	52180	0	0	0
T39	1374	0	0	0
T41	0	5	0	0
T47	0	4	0	0
T48	0	5	0	0
T75	0	7	0	0
T76	0	3	0	0
T77	0	2	0	0
T78	0	18	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	14611	0	0
T2	34844	32	0	0
T3	4640	0	0	0
T4	23481	41	0	0
T5	29537	75	0	0
T6	378922	340	0	0
T7	14761	15	0	0
T8	1582	1	0	0
T9	29140	75	0	0
T10	3719	0	0	0
T11	29402	75	0	0
T20	0	4	0	0
T21	0	419	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	1094	0	0
T6	378922	18	0	0
T7	14761	9	0	0
T8	1582	0	0	0
T9	29140	0	0	0
T10	3719	0	0	0
T11	29402	0	0	0
T20	2830	0	0	0
T21	244632	7	0	0
T22	52180	0	0	0
T39	1374	0	0	0
T41	0	5	0	0
T47	0	4	0	0
T48	0	5	0	0
T75	0	7	0	0
T76	0	3	0	0
T77	0	2	0	0
T78	0	18	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55609468	13239	0	0
T2	139376	26	0	0
T3	18569	0	0	0
T4	93927	37	0	0
T5	118182	70	0	0
T6	151557	314	0	0
T7	59039	14	0	0
T8	6333	1	0	0
T9	116567	67	0	0
T10	14885	0	0	0
T11	117577	68	0	0
T20	0	3	0	0
T21	0	376	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55609468	1083	0	0
T6	151557	20	0	0
T7	59039	7	0	0
T8	6333	0	0	0
T9	116567	0	0	0
T10	14885	0	0	0
T11	117577	0	0	0
T20	11324	0	0	0
T21	978441	9	0	0
T22	208747	0	0	0
T39	5499	0	0	0
T41	0	6	0	0
T47	0	6	0	0
T48	0	7	0	0
T52	0	1	0	0
T75	0	8	0	0
T76	0	2	0	0
T78	0	24	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55609468	13239	0	0
T2	139376	26	0	0
T3	18569	0	0	0
T4	93927	37	0	0
T5	118182	70	0	0
T6	151557	314	0	0
T7	59039	14	0	0
T8	6333	1	0	0
T9	116567	67	0	0
T10	14885	0	0	0
T11	117577	68	0	0
T20	0	3	0	0
T21	0	376	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55609468	1083	0	0
T6	151557	20	0	0
T7	59039	7	0	0
T8	6333	0	0	0
T9	116567	0	0	0
T10	14885	0	0	0
T11	117577	0	0	0
T20	11324	0	0	0
T21	978441	9	0	0
T22	208747	0	0	0
T39	5499	0	0	0
T41	0	6	0	0
T47	0	6	0	0
T48	0	7	0	0
T52	0	1	0	0
T75	0	8	0	0
T76	0	2	0	0
T78	0	24	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805487	13301	0	0
T2	69689	26	0	0
T3	9284	0	0	0
T4	46964	37	0	0
T5	59082	70	0	0
T6	757834	312	0	0
T7	29523	13	0	0
T8	3165	1	0	0
T9	58265	67	0	0
T10	7443	0	0	0
T11	58791	68	0	0
T20	0	4	0	0
T21	0	374	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805487	1106	0	0
T6	757834	17	0	0
T7	29523	8	0	0
T8	3165	0	0	0
T9	58265	0	0	0
T10	7443	0	0	0
T11	58791	0	0	0
T20	5665	1	0	0
T21	489250	7	0	0
T22	104372	0	0	0
T39	2749	0	0	0
T41	0	7	0	0
T47	0	6	0	0
T48	0	8	0	0
T75	0	5	0	0
T76	0	1	0	0
T78	0	20	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805487	13301	0	0
T2	69689	26	0	0
T3	9284	0	0	0
T4	46964	37	0	0
T5	59082	70	0	0
T6	757834	312	0	0
T7	29523	13	0	0
T8	3165	1	0	0
T9	58265	67	0	0
T10	7443	0	0	0
T11	58791	68	0	0
T20	0	4	0	0
T21	0	374	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805487	1106	0	0
T6	757834	17	0	0
T7	29523	8	0	0
T8	3165	0	0	0
T9	58265	0	0	0
T10	7443	0	0	0
T11	58791	0	0	0
T20	5665	1	0	0
T21	489250	7	0	0
T22	104372	0	0	0
T39	2749	0	0	0
T41	0	7	0	0
T47	0	6	0	0
T48	0	8	0	0
T75	0	5	0	0
T76	0	1	0	0
T78	0	20	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805480	13335	0	0
T2	69687	26	0	0
T3	9284	0	0	0
T4	46969	37	0	0
T5	59076	70	0	0
T6	757811	311	0	0
T7	29523	16	0	0
T8	3165	1	0	0
T9	58270	67	0	0
T10	7442	0	0	0
T11	58788	68	0	0
T20	0	3	0	0
T21	0	374	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805480	1124	0	0
T6	757811	16	0	0
T7	29523	10	0	0
T8	3165	0	0	0
T9	58270	0	0	0
T10	7442	0	0	0
T11	58788	0	0	0
T20	5664	0	0	0
T21	489240	6	0	0
T22	104356	0	0	0
T39	2749	0	0	0
T41	0	8	0	0
T47	0	8	0	0
T48	0	9	0	0
T75	0	6	0	0
T76	0	3	0	0
T78	0	20	0	0
T79	0	8	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805480	13335	0	0
T2	69687	26	0	0
T3	9284	0	0	0
T4	46969	37	0	0
T5	59076	70	0	0
T6	757811	311	0	0
T7	29523	16	0	0
T8	3165	1	0	0
T9	58270	67	0	0
T10	7442	0	0	0
T11	58788	68	0	0
T20	0	3	0	0
T21	0	374	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27805480	1124	0	0
T6	757811	16	0	0
T7	29523	10	0	0
T8	3165	0	0	0
T9	58270	0	0	0
T10	7442	0	0	0
T11	58788	0	0	0
T20	5664	0	0	0
T21	489240	6	0	0
T22	104356	0	0	0
T39	2749	0	0	0
T41	0	8	0	0
T47	0	8	0	0
T48	0	9	0	0
T75	0	6	0	0
T76	0	3	0	0
T78	0	20	0	0
T79	0	8	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1755818	22989	0	0
T1	204	1	0	0
T2	4412	50	0	0
T3	580	2	0	0
T4	3036	61	0	0
T5	3707	76	0	0
T6	48080	514	0	0
T7	1844	20	0	0
T8	197	2	0	0
T9	3658	74	0	0
T10	463	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1755818	1205	0	0
T6	48080	18	0	0
T7	1844	9	0	0
T8	197	0	0	0
T9	3658	0	0	0
T10	463	0	0	0
T11	3689	0	0	0
T20	353	1	0	0
T21	31302	9	0	0
T22	6537	0	0	0
T39	171	0	0	0
T41	0	8	0	0
T47	0	11	0	0
T48	0	11	0	0
T75	0	6	0	0
T76	0	2	0	0
T78	0	21	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1755818	22989	0	0
T1	204	1	0	0
T2	4412	50	0	0
T3	580	2	0	0
T4	3036	61	0	0
T5	3707	76	0	0
T6	48080	514	0	0
T7	1844	20	0	0
T8	197	2	0	0
T9	3658	74	0	0
T10	463	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1755818	1205	0	0
T6	48080	18	0	0
T7	1844	9	0	0
T8	197	0	0	0
T9	3658	0	0	0
T10	463	0	0	0
T11	3689	0	0	0
T20	353	1	0	0
T21	31302	9	0	0
T22	6537	0	0	0
T39	171	0	0	0
T41	0	8	0	0
T47	0	11	0	0
T48	0	11	0	0
T75	0	6	0	0
T76	0	2	0	0
T78	0	21	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	14873	0	0
T2	34844	32	0	0
T3	4640	0	0	0
T4	23481	41	0	0
T5	29537	75	0	0
T6	378922	341	0	0
T7	14761	14	0	0
T8	1582	1	0	0
T9	29140	75	0	0
T10	3719	0	0	0
T11	29402	75	0	0
T20	0	4	0	0
T21	0	421	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	1234	0	0
T6	378922	18	0	0
T7	14761	8	0	0
T8	1582	0	0	0
T9	29140	0	0	0
T10	3719	0	0	0
T11	29402	0	0	0
T20	2830	0	0	0
T21	244632	8	0	0
T22	52180	0	0	0
T39	1374	0	0	0
T41	0	9	0	0
T47	0	9	0	0
T48	0	13	0	0
T75	0	7	0	0
T76	0	2	0	0
T78	0	23	0	0
T79	0	12	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	14873	0	0
T2	34844	32	0	0
T3	4640	0	0	0
T4	23481	41	0	0
T5	29537	75	0	0
T6	378922	341	0	0
T7	14761	14	0	0
T8	1582	1	0	0
T9	29140	75	0	0
T10	3719	0	0	0
T11	29402	75	0	0
T20	0	4	0	0
T21	0	421	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	1234	0	0
T6	378922	18	0	0
T7	14761	8	0	0
T8	1582	0	0	0
T9	29140	0	0	0
T10	3719	0	0	0
T11	29402	0	0	0
T20	2830	0	0	0
T21	244632	8	0	0
T22	52180	0	0	0
T39	1374	0	0	0
T41	0	9	0	0
T47	0	9	0	0
T48	0	13	0	0
T75	0	7	0	0
T76	0	2	0	0
T78	0	23	0	0
T79	0	12	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	14940	0	0
T2	34844	32	0	0
T3	4640	0	0	0
T4	23481	41	0	0
T5	29537	75	0	0
T6	378922	340	0	0
T7	14761	14	0	0
T8	1582	1	0	0
T9	29140	75	0	0
T10	3719	0	0	0
T11	29402	75	0	0
T20	0	5	0	0
T21	0	420	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	1298	0	0
T6	378922	17	0	0
T7	14761	8	0	0
T8	1582	0	0	0
T9	29140	0	0	0
T10	3719	0	0	0
T11	29402	0	0	0
T20	2830	1	0	0
T21	244632	7	0	0
T22	52180	0	0	0
T39	1374	0	0	0
T41	0	10	0	0
T47	0	12	0	0
T48	0	13	0	0
T52	0	1	0	0
T75	0	7	0	0
T76	0	2	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	14940	0	0
T2	34844	32	0	0
T3	4640	0	0	0
T4	23481	41	0	0
T5	29537	75	0	0
T6	378922	340	0	0
T7	14761	14	0	0
T8	1582	1	0	0
T9	29140	75	0	0
T10	3719	0	0	0
T11	29402	75	0	0
T20	0	5	0	0
T21	0	420	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	1298	0	0
T6	378922	17	0	0
T7	14761	8	0	0
T8	1582	0	0	0
T9	29140	0	0	0
T10	3719	0	0	0
T11	29402	0	0	0
T20	2830	1	0	0
T21	244632	7	0	0
T22	52180	0	0	0
T39	1374	0	0	0
T41	0	10	0	0
T47	0	12	0	0
T48	0	13	0	0
T52	0	1	0	0
T75	0	7	0	0
T76	0	2	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	14961	0	0
T2	34844	32	0	0
T3	4640	0	0	0
T4	23481	41	0	0
T5	29537	75	0	0
T6	378922	339	0	0
T7	14761	15	0	0
T8	1582	1	0	0
T9	29140	75	0	0
T10	3719	0	0	0
T11	29402	75	0	0
T20	0	5	0	0
T21	0	421	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	1326	0	0
T6	378922	17	0	0
T7	14761	11	0	0
T8	1582	0	0	0
T9	29140	0	0	0
T10	3719	0	0	0
T11	29402	0	0	0
T20	2830	1	0	0
T21	244632	8	0	0
T22	52180	0	0	0
T39	1374	0	0	0
T41	0	10	0	0
T47	0	13	0	0
T48	0	14	0	0
T75	0	9	0	0
T76	0	2	0	0
T78	0	20	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	14961	0	0
T2	34844	32	0	0
T3	4640	0	0	0
T4	23481	41	0	0
T5	29537	75	0	0
T6	378922	339	0	0
T7	14761	15	0	0
T8	1582	1	0	0
T9	29140	75	0	0
T10	3719	0	0	0
T11	29402	75	0	0
T20	0	5	0	0
T21	0	421	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13902597	1326	0	0
T6	378922	17	0	0
T7	14761	11	0	0
T8	1582	0	0	0
T9	29140	0	0	0
T10	3719	0	0	0
T11	29402	0	0	0
T20	2830	1	0	0
T21	244632	8	0	0
T22	52180	0	0	0
T39	1374	0	0	0
T41	0	10	0	0
T47	0	13	0	0
T48	0	14	0	0
T75	0	9	0	0
T76	0	2	0	0
T78	0	20	0	0