Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13137272	8114	0	0
alert_regwen_rd_A	13137272	5504	0	0
cpu_regwen_rd_A	13137272	5619	0	0
sw_rst_ctrl_n_0_rd_A	13137272	10247	0	0
sw_rst_ctrl_n_1_rd_A	13137272	10009	0	0
sw_rst_ctrl_n_2_rd_A	13137272	9483	0	0
sw_rst_ctrl_n_3_rd_A	13137272	9775	0	0
sw_rst_ctrl_n_4_rd_A	13137272	9991	0	0
sw_rst_ctrl_n_5_rd_A	13137272	9687	0	0
sw_rst_ctrl_n_6_rd_A	13137272	9952	0	0
sw_rst_ctrl_n_7_rd_A	13137272	9987	0	0
sw_rst_regwen_0_rd_A	13137272	5936	0	0
sw_rst_regwen_1_rd_A	13137272	5852	0	0
sw_rst_regwen_2_rd_A	13137272	6046	0	0
sw_rst_regwen_3_rd_A	13137272	6051	0	0
sw_rst_regwen_4_rd_A	13137272	6105	0	0
sw_rst_regwen_5_rd_A	13137272	5869	0	0
sw_rst_regwen_6_rd_A	13137272	5847	0	0
sw_rst_regwen_7_rd_A	13137272	6123	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	8114	0	0
T51	18368	1	0	0
T53	10831	515	0	0
T54	4883	660	0	0
T55	3372	16	0	0
T56	9697	1	0	0
T81	2724	102	0	0
T82	4579	27	0	0
T84	21574	4	0	0
T85	6491	128	0	0
T89	10173	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	5504	0	0
T6	334035	319	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	39	0	0
T39	1283	0	0	0
T78	0	77	0	0
T90	0	59	0	0
T92	0	24	0	0
T93	0	68	0	0
T94	0	551	0	0
T95	0	33	0	0
T115	0	88	0	0
T116	0	69	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	5619	0	0
T6	334035	342	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	25	0	0
T39	1283	0	0	0
T78	0	90	0	0
T90	0	65	0	0
T92	0	21	0	0
T93	0	76	0	0
T94	0	518	0	0
T95	0	33	0	0
T115	0	114	0	0
T116	0	50	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	10247	0	0
T6	334035	578	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	17	0	0
T39	1283	0	0	0
T42	0	35	0	0
T78	0	293	0	0
T90	0	77	0	0
T92	0	28	0	0
T93	0	89	0	0
T94	0	739	0	0
T95	0	43	0	0
T115	0	730	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	10009	0	0
T6	334035	505	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	25	0	0
T39	1283	0	0	0
T42	0	52	0	0
T78	0	216	0	0
T90	0	79	0	0
T92	0	25	0	0
T93	0	67	0	0
T94	0	786	0	0
T95	0	26	0	0
T115	0	668	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	9483	0	0
T6	334035	455	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	32	0	0
T39	1283	0	0	0
T42	0	37	0	0
T78	0	230	0	0
T90	0	53	0	0
T92	0	20	0	0
T93	0	50	0	0
T94	0	704	0	0
T95	0	34	0	0
T115	0	661	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	9775	0	0
T6	334035	399	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	44	0	0
T39	1283	0	0	0
T42	0	49	0	0
T78	0	237	0	0
T90	0	76	0	0
T92	0	42	0	0
T93	0	85	0	0
T94	0	769	0	0
T95	0	60	0	0
T115	0	658	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	9991	0	0
T6	334035	410	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	42	0	0
T39	1283	0	0	0
T42	0	38	0	0
T78	0	246	0	0
T90	0	75	0	0
T92	0	42	0	0
T93	0	67	0	0
T94	0	740	0	0
T95	0	39	0	0
T115	0	683	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	9687	0	0
T6	334035	455	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	53	0	0
T39	1283	0	0	0
T42	0	41	0	0
T78	0	194	0	0
T90	0	77	0	0
T92	0	13	0	0
T93	0	63	0	0
T94	0	725	0	0
T95	0	42	0	0
T115	0	671	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	9952	0	0
T6	334035	496	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	34	0	0
T39	1283	0	0	0
T42	0	35	0	0
T78	0	252	0	0
T90	0	101	0	0
T92	0	25	0	0
T93	0	76	0	0
T94	0	762	0	0
T95	0	35	0	0
T115	0	684	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	9987	0	0
T6	334035	554	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	38	0	0
T39	1283	0	0	0
T42	0	31	0	0
T78	0	224	0	0
T90	0	73	0	0
T92	0	48	0	0
T93	0	62	0	0
T94	0	713	0	0
T95	0	37	0	0
T115	0	717	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	5936	0	0
T6	334035	368	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	39	0	0
T39	1283	0	0	0
T78	0	75	0	0
T90	0	101	0	0
T92	0	21	0	0
T93	0	54	0	0
T94	0	547	0	0
T95	0	25	0	0
T115	0	108	0	0
T116	0	46	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	5852	0	0
T6	334035	370	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	36	0	0
T39	1283	0	0	0
T78	0	51	0	0
T90	0	81	0	0
T92	0	35	0	0
T93	0	61	0	0
T94	0	525	0	0
T95	0	26	0	0
T115	0	119	0	0
T116	0	28	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	6046	0	0
T6	334035	329	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	27	0	0
T39	1283	0	0	0
T78	0	63	0	0
T90	0	70	0	0
T92	0	44	0	0
T93	0	67	0	0
T94	0	499	0	0
T95	0	8	0	0
T115	0	136	0	0
T116	0	38	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	6051	0	0
T6	334035	405	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	62	0	0
T39	1283	0	0	0
T78	0	61	0	0
T90	0	65	0	0
T92	0	42	0	0
T93	0	59	0	0
T94	0	506	0	0
T95	0	48	0	0
T115	0	91	0	0
T116	0	71	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	6105	0	0
T6	334035	344	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	34	0	0
T39	1283	0	0	0
T78	0	65	0	0
T90	0	74	0	0
T92	0	13	0	0
T93	0	61	0	0
T94	0	566	0	0
T95	0	34	0	0
T115	0	142	0	0
T116	0	69	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	5869	0	0
T6	334035	341	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	34	0	0
T39	1283	0	0	0
T78	0	68	0	0
T90	0	68	0	0
T92	0	28	0	0
T93	0	59	0	0
T94	0	505	0	0
T95	0	20	0	0
T115	0	97	0	0
T116	0	76	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	5847	0	0
T6	334035	323	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	12	0	0
T39	1283	0	0	0
T78	0	77	0	0
T90	0	83	0	0
T92	0	46	0	0
T93	0	62	0	0
T94	0	547	0	0
T95	0	26	0	0
T115	0	131	0	0
T116	0	68	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13137272	6123	0	0
T6	334035	382	0	0
T7	14159	0	0	0
T8	1439	0	0	0
T9	25966	0	0	0
T10	3558	0	0	0
T11	25961	0	0	0
T20	2444	0	0	0
T21	188092	0	0	0
T22	48925	0	0	0
T34	0	39	0	0
T39	1283	0	0	0
T78	0	125	0	0
T90	0	70	0	0
T92	0	9	0	0
T93	0	81	0	0
T94	0	542	0	0
T95	0	52	0	0
T115	0	82	0	0
T116	0	31	0	0