Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	605602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

363369

1

T1

73

T2

132

T4

1137

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	515503	1			T1	99		T2	186		T4	1500
values[0x0]	226728	1			T1	50		T2	101		T4	862
values[0x1]	226740	1			T1	63		T2	92		T4	838

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	508269	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

460702

1

T1

95

T2

166

T4

1453

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4223	1			T1	3		T8	15		T9	24
valid_sources[0x01]	4160	1			T8	18		T9	64		T10	4
valid_sources[0x02]	3725	1			T8	9		T9	39		T10	16
valid_sources[0x03]	3048	1			T8	7		T9	41		T10	5
valid_sources[0x04]	3796	1			T8	17		T9	22		T10	11
valid_sources[0x05]	7074	1			T1	1		T8	7		T9	27
valid_sources[0x06]	3414	1			T1	1		T8	6		T9	42
valid_sources[0x07]	3690	1			T1	1		T8	11		T9	21
valid_sources[0x08]	3301	1			T8	21		T9	66		T10	12
valid_sources[0x09]	4522	1			T1	1		T8	12		T9	19
valid_sources[0x0a]	3166	1			T1	4		T2	3		T8	15
valid_sources[0x0b]	2775	1			T8	16		T9	25		T10	16
valid_sources[0x0c]	3040	1			T1	1		T8	14		T9	29
valid_sources[0x0d]	2864	1			T1	2		T8	22		T9	40
valid_sources[0x0e]	3189	1			T8	12		T9	41		T10	15
valid_sources[0x0f]	2765	1			T8	15		T9	51		T10	9
valid_sources[0x10]	3179	1			T6	2		T8	6		T9	34
valid_sources[0x11]	6940	1			T8	18		T9	23		T10	12
valid_sources[0x12]	3278	1			T8	10		T9	21		T10	6
valid_sources[0x13]	3786	1			T8	18		T9	51		T10	10
valid_sources[0x14]	3672	1			T2	9		T8	18		T9	44
valid_sources[0x15]	3152	1			T8	20		T9	45		T10	3
valid_sources[0x16]	6590	1			T1	2		T8	6		T9	34
valid_sources[0x17]	3382	1			T1	2		T8	10		T9	48
valid_sources[0x18]	3477	1			T1	1		T8	16		T9	48
valid_sources[0x19]	2952	1			T8	20		T9	27		T10	8
valid_sources[0x1a]	6698	1			T1	2		T2	13		T7	3200
valid_sources[0x1b]	3000	1			T1	2		T8	6		T9	47
valid_sources[0x1c]	4629	1			T8	11		T9	47		T10	6
valid_sources[0x1d]	4028	1			T8	6		T9	52		T10	4
valid_sources[0x1e]	4175	1			T1	2		T8	21		T9	38
valid_sources[0x1f]	4141	1			T8	13		T9	48		T10	19
valid_sources[0x20]	2627	1			T1	2		T8	11		T9	27
valid_sources[0x21]	3750	1			T1	2		T8	8		T9	33
valid_sources[0x22]	3208	1			T8	15		T9	48		T10	3
valid_sources[0x23]	3776	1			T8	8		T9	43		T10	10
valid_sources[0x24]	6576	1			T2	3		T8	8		T9	47
valid_sources[0x25]	3418	1			T8	9		T9	45		T10	13
valid_sources[0x26]	3284	1			T2	12		T8	15		T9	34
valid_sources[0x27]	3025	1			T8	17		T9	52		T10	18
valid_sources[0x28]	2759	1			T1	2		T8	18		T9	24
valid_sources[0x29]	3110	1			T1	1		T8	18		T9	51
valid_sources[0x2a]	4268	1			T8	28		T9	53		T10	6
valid_sources[0x2b]	2926	1			T6	1		T8	17		T9	56
valid_sources[0x2c]	3550	1			T8	14		T9	55		T10	12
valid_sources[0x2d]	4358	1			T1	1		T8	9		T9	33
valid_sources[0x2e]	3283	1			T8	19		T9	51		T10	11
valid_sources[0x2f]	3133	1			T8	13		T9	44		T10	13
valid_sources[0x30]	3125	1			T1	2		T8	20		T9	59
valid_sources[0x31]	6435	1			T8	10		T9	43		T10	9
valid_sources[0x32]	4152	1			T1	1		T8	5		T9	42
valid_sources[0x33]	3858	1			T1	1		T8	21		T9	21
valid_sources[0x34]	3212	1			T8	14		T9	44		T10	14
valid_sources[0x35]	3261	1			T1	2		T8	6		T9	36
valid_sources[0x36]	3034	1			T8	20		T9	36		T10	11
valid_sources[0x37]	4202	1			T8	11		T9	34		T10	19
valid_sources[0x38]	3372	1			T1	1		T8	11		T9	48
valid_sources[0x39]	3753	1			T1	2		T8	19		T9	44
valid_sources[0x3a]	4705	1			T6	4		T8	18		T9	52
valid_sources[0x3b]	3544	1			T1	1		T8	13		T9	58
valid_sources[0x3c]	4386	1			T1	2		T2	7		T8	21
valid_sources[0x3d]	4055	1			T1	2		T2	15		T8	18
valid_sources[0x3e]	3492	1			T2	6		T8	24		T9	39
valid_sources[0x3f]	3249	1			T1	1		T8	11		T9	47
valid_sources[0x40]	3905	1			T1	2		T8	19		T9	36
valid_sources[0x41]	3075	1			T1	1		T8	17		T9	47
valid_sources[0x42]	3293	1			T1	2		T8	10		T9	52
valid_sources[0x43]	5416	1			T2	7		T8	5		T9	29
valid_sources[0x44]	4452	1			T8	11		T9	37		T10	10
valid_sources[0x45]	3846	1			T2	2		T6	1		T8	5
valid_sources[0x46]	3860	1			T8	16		T9	48		T10	24
valid_sources[0x47]	4185	1			T8	7		T9	41		T10	13
valid_sources[0x48]	3191	1			T1	1		T2	7		T6	2
valid_sources[0x49]	4060	1			T1	1		T8	14		T9	39
valid_sources[0x4a]	3101	1			T1	2		T8	6		T9	41
valid_sources[0x4b]	3485	1			T1	2		T8	2		T9	27
valid_sources[0x4c]	3127	1			T2	7		T8	10		T9	43
valid_sources[0x4d]	3594	1			T1	1		T2	1		T8	10
valid_sources[0x4e]	3405	1			T8	7		T9	45		T10	6
valid_sources[0x4f]	2884	1			T1	1		T8	11		T9	54
valid_sources[0x50]	2998	1			T1	1		T8	13		T9	26
valid_sources[0x51]	3356	1			T8	18		T9	36		T10	6
valid_sources[0x52]	3440	1			T1	1		T8	19		T9	36
valid_sources[0x53]	3833	1			T1	2		T8	14		T9	28
valid_sources[0x54]	4186	1			T1	2		T8	14		T9	56
valid_sources[0x55]	4490	1			T1	1		T2	3		T8	15
valid_sources[0x56]	4060	1			T2	7		T8	6		T9	31
valid_sources[0x57]	3662	1			T1	1		T2	15		T6	2
valid_sources[0x58]	4210	1			T1	1		T8	11		T9	33
valid_sources[0x59]	3890	1			T1	2		T8	20		T9	45
valid_sources[0x5a]	3602	1			T1	1		T2	10		T8	19
valid_sources[0x5b]	3566	1			T1	1		T8	5		T9	50
valid_sources[0x5c]	3364	1			T8	11		T9	32		T10	8
valid_sources[0x5d]	2822	1			T8	13		T9	42		T10	7
valid_sources[0x5e]	3325	1			T1	2		T8	16		T9	33
valid_sources[0x5f]	3235	1			T8	7		T9	52		T10	16
valid_sources[0x60]	3692	1			T1	1		T8	14		T9	37
valid_sources[0x61]	3319	1			T2	3		T8	19		T9	60
valid_sources[0x62]	3039	1			T8	6		T9	39		T10	13
valid_sources[0x63]	4602	1			T1	1		T8	13		T9	54
valid_sources[0x64]	3660	1			T1	1		T8	19		T9	39
valid_sources[0x65]	3874	1			T1	1		T2	4		T8	19
valid_sources[0x66]	3061	1			T1	1		T8	20		T9	37
valid_sources[0x67]	3408	1			T1	1		T2	8		T8	9
valid_sources[0x68]	3045	1			T2	1		T8	17		T9	39
valid_sources[0x69]	3722	1			T8	14		T9	20		T10	16
valid_sources[0x6a]	2748	1			T2	2		T8	5		T9	52
valid_sources[0x6b]	3190	1			T1	2		T2	4		T8	8
valid_sources[0x6c]	3227	1			T1	3		T8	17		T9	68
valid_sources[0x6d]	4599	1			T8	26		T9	43		T10	17
valid_sources[0x6e]	3740	1			T1	1		T8	12		T9	50
valid_sources[0x6f]	3822	1			T1	2		T2	8		T8	7
valid_sources[0x70]	3353	1			T1	2		T8	18		T9	37
valid_sources[0x71]	3661	1			T8	12		T9	48		T10	3
valid_sources[0x72]	8528	1			T4	3200		T8	12		T9	41
valid_sources[0x73]	3882	1			T1	1		T8	12		T9	39
valid_sources[0x74]	4201	1			T1	1		T9	32		T10	14
valid_sources[0x75]	2877	1			T1	1		T8	16		T9	38
valid_sources[0x76]	3591	1			T1	1		T8	6		T9	46
valid_sources[0x77]	2809	1			T1	1		T8	2		T9	49
valid_sources[0x78]	3975	1			T1	3		T8	9		T9	45
valid_sources[0x79]	3704	1			T1	1		T8	9		T9	53
valid_sources[0x7a]	3044	1			T1	1		T8	13		T9	16
valid_sources[0x7b]	6370	1			T1	3		T8	7		T9	42
valid_sources[0x7c]	3454	1			T1	1		T2	4		T8	6
valid_sources[0x7d]	4448	1			T1	1		T2	4		T8	14
valid_sources[0x7e]	4332	1			T2	4		T8	19		T9	20
valid_sources[0x7f]	3738	1			T8	8		T9	38		T10	22
valid_sources[0x80]	6741	1			T1	1		T8	19		T9	47

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

241601

1

T1

46

T2

80

T4

706

values[0x0]

all_enables

biggest_size

79274

1

T1

16

T2

33

T4

306

values[0x1]

all_enables

biggest_size

42494

1

T1

11

T2

19

T4

125