Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T9
0	1	Covered	T1,T9,T10
1	0	Covered	T2,T9,T10

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54200386	8727	0	0
CascadeEffAonToRstPorAboveRise_A	54200386	8727	0	0
CascadeEffAonToRstPorIoAboveFall_A	52030628	8727	0	0
CascadeEffAonToRstPorIoAboveRise_A	52030628	8727	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26016409	8727	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26016409	8727	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13007859	8727	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13007859	8727	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26016262	8727	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26016262	8727	0	0
CascadeLcToLcAboveFall_A	54200386	21772	0	0
CascadeLcToLcAboveRise_A	54200386	21772	0	0
CascadeLcToLcAonAboveFall_A	1641933	21772	0	0
CascadeLcToLcAonAboveRise_A	1641933	21772	0	0
CascadeLcToLcShadowedAboveFall_A	54200386	21772	0	0
CascadeLcToLcShadowedAboveRise_A	54200386	21772	0	0
CascadePorToAonAboveFall_A	1641933	7080	0	0
CascadeSysToSysAboveFall_A	54200386	21772	0	0
CascadeSysToSysAboveRise_A	54200386	21772	0	0
ScanRstToAonRise_A	1641933	199	0	0
StablePorToAonRise_A	1641933	8727	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11550997	21772	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11550997	21772	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11550997	21772	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11550997	21772	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13007859	21772	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13007859	21772	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11550997	21772	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11550997	21772	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11550997	21772	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11550997	21772	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54200386	8727	0	0
T1	9954	2	0	0
T2	11585	2	0	0
T3	24280	8	0	0
T4	189963	27	0	0
T5	24269	8	0	0
T6	168502	541	0	0
T7	121782	27	0	0
T8	188387	27	0	0
T9	557326	67	0	0
T10	161464	21	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54200386	8727	0	0
T1	9954	2	0	0
T2	11585	2	0	0
T3	24280	8	0	0
T4	189963	27	0	0
T5	24269	8	0	0
T6	168502	541	0	0
T7	121782	27	0	0
T8	188387	27	0	0
T9	557326	67	0	0
T10	161464	21	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52030628	8727	0	0
T1	9549	2	0	0
T2	11117	2	0	0
T3	23308	8	0	0
T4	182359	27	0	0
T5	23302	8	0	0
T6	161746	541	0	0
T7	116875	27	0	0
T8	180861	27	0	0
T9	535041	67	0	0
T10	155000	21	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52030628	8727	0	0
T1	9549	2	0	0
T2	11117	2	0	0
T3	23308	8	0	0
T4	182359	27	0	0
T5	23302	8	0	0
T6	161746	541	0	0
T7	116875	27	0	0
T8	180861	27	0	0
T9	535041	67	0	0
T10	155000	21	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016409	8727	0	0
T1	4772	2	0	0
T2	5556	2	0	0
T3	11648	8	0	0
T4	91200	27	0	0
T5	11656	8	0	0
T6	808792	541	0	0
T7	58441	27	0	0
T8	90427	27	0	0
T9	267509	67	0	0
T10	77504	21	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016409	8727	0	0
T1	4772	2	0	0
T2	5556	2	0	0
T3	11648	8	0	0
T4	91200	27	0	0
T5	11656	8	0	0
T6	808792	541	0	0
T7	58441	27	0	0
T8	90427	27	0	0
T9	267509	67	0	0
T10	77504	21	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	8727	0	0
T1	2386	2	0	0
T2	2778	2	0	0
T3	5826	8	0	0
T4	45597	27	0	0
T5	5824	8	0	0
T6	404350	541	0	0
T7	29233	27	0	0
T8	45210	27	0	0
T9	133758	67	0	0
T10	38746	21	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	8727	0	0
T1	2386	2	0	0
T2	2778	2	0	0
T3	5826	8	0	0
T4	45597	27	0	0
T5	5824	8	0	0
T6	404350	541	0	0
T7	29233	27	0	0
T8	45210	27	0	0
T9	133758	67	0	0
T10	38746	21	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016262	8727	0	0
T1	4775	2	0	0
T2	5559	2	0	0
T3	11647	8	0	0
T4	91184	27	0	0
T5	11649	8	0	0
T6	808847	541	0	0
T7	58452	27	0	0
T8	90438	27	0	0
T9	267501	67	0	0
T10	77501	21	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016262	8727	0	0
T1	4775	2	0	0
T2	5559	2	0	0
T3	11647	8	0	0
T4	91184	27	0	0
T5	11649	8	0	0
T6	808847	541	0	0
T7	58452	27	0	0
T8	90438	27	0	0
T9	267501	67	0	0
T10	77501	21	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54200386	21772	0	0
T1	9954	6	0	0
T2	11585	6	0	0
T3	24280	8	0	0
T4	189963	102	0	0
T5	24269	8	0	0
T6	168502	541	0	0
T7	121782	102	0	0
T8	188387	102	0	0
T9	557326	205	0	0
T10	161464	61	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54200386	21772	0	0
T1	9954	6	0	0
T2	11585	6	0	0
T3	24280	8	0	0
T4	189963	102	0	0
T5	24269	8	0	0
T6	168502	541	0	0
T7	121782	102	0	0
T8	188387	102	0	0
T9	557326	205	0	0
T10	161464	61	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641933	21772	0	0
T1	297	6	0	0
T2	346	6	0	0
T3	730	8	0	0
T4	5714	102	0	0
T5	730	8	0	0
T6	50795	541	0	0
T7	3668	102	0	0
T8	5665	102	0	0
T9	16945	205	0	0
T10	4908	61	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641933	21772	0	0
T1	297	6	0	0
T2	346	6	0	0
T3	730	8	0	0
T4	5714	102	0	0
T5	730	8	0	0
T6	50795	541	0	0
T7	3668	102	0	0
T8	5665	102	0	0
T9	16945	205	0	0
T10	4908	61	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54200386	21772	0	0
T1	9954	6	0	0
T2	11585	6	0	0
T3	24280	8	0	0
T4	189963	102	0	0
T5	24269	8	0	0
T6	168502	541	0	0
T7	121782	102	0	0
T8	188387	102	0	0
T9	557326	205	0	0
T10	161464	61	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54200386	21772	0	0
T1	9954	6	0	0
T2	11585	6	0	0
T3	24280	8	0	0
T4	189963	102	0	0
T5	24269	8	0	0
T6	168502	541	0	0
T7	121782	102	0	0
T8	188387	102	0	0
T9	557326	205	0	0
T10	161464	61	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641933	7080	0	0
T1	297	1	0	0
T2	346	1	0	0
T3	730	8	0	0
T4	5714	27	0	0
T5	730	8	0	0
T6	50795	541	0	0
T7	3668	27	0	0
T8	5665	27	0	0
T9	16945	34	0	0
T10	4908	11	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54200386	21772	0	0
T1	9954	6	0	0
T2	11585	6	0	0
T3	24280	8	0	0
T4	189963	102	0	0
T5	24269	8	0	0
T6	168502	541	0	0
T7	121782	102	0	0
T8	188387	102	0	0
T9	557326	205	0	0
T10	161464	61	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54200386	21772	0	0
T1	9954	6	0	0
T2	11585	6	0	0
T3	24280	8	0	0
T4	189963	102	0	0
T5	24269	8	0	0
T6	168502	541	0	0
T7	121782	102	0	0
T8	188387	102	0	0
T9	557326	205	0	0
T10	161464	61	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641933	199	0	0
T9	16945	2	0	0
T10	4908	1	0	0
T11	319	0	0	0
T12	693	0	0	0
T13	5760	1	0	0
T23	424	0	0	0
T24	654	0	0	0
T25	288	0	0	0
T26	3008	1	0	0
T28	0	1	0	0
T39	182	0	0	0
T67	0	2	0	0
T70	0	6	0	0
T83	0	1	0	0
T84	0	1	0	0
T117	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641933	8727	0	0
T1	297	2	0	0
T2	346	2	0	0
T3	730	8	0	0
T4	5714	27	0	0
T5	730	8	0	0
T6	50795	541	0	0
T7	3668	27	0	0
T8	5665	27	0	0
T9	16945	67	0	0
T10	4908	21	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11550997	21772	0	0
T1	2147	6	0	0
T2	2584	6	0	0
T3	5089	8	0	0
T4	42340	102	0	0
T5	5472	8	0	0
T6	354431	541	0	0
T7	26050	102	0	0
T8	42044	102	0	0
T9	116368	205	0	0
T10	33648	61	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11550997	21772	0	0
T1	2147	6	0	0
T2	2584	6	0	0
T3	5089	8	0	0
T4	42340	102	0	0
T5	5472	8	0	0
T6	354431	541	0	0
T7	26050	102	0	0
T8	42044	102	0	0
T9	116368	205	0	0
T10	33648	61	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11550997	21772	0	0
T1	2147	6	0	0
T2	2584	6	0	0
T3	5089	8	0	0
T4	42340	102	0	0
T5	5472	8	0	0
T6	354431	541	0	0
T7	26050	102	0	0
T8	42044	102	0	0
T9	116368	205	0	0
T10	33648	61	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11550997	21772	0	0
T1	2147	6	0	0
T2	2584	6	0	0
T3	5089	8	0	0
T4	42340	102	0	0
T5	5472	8	0	0
T6	354431	541	0	0
T7	26050	102	0	0
T8	42044	102	0	0
T9	116368	205	0	0
T10	33648	61	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	21772	0	0
T1	2386	6	0	0
T2	2778	6	0	0
T3	5826	8	0	0
T4	45597	102	0	0
T5	5824	8	0	0
T6	404350	541	0	0
T7	29233	102	0	0
T8	45210	102	0	0
T9	133758	205	0	0
T10	38746	61	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	21772	0	0
T1	2386	6	0	0
T2	2778	6	0	0
T3	5826	8	0	0
T4	45597	102	0	0
T5	5824	8	0	0
T6	404350	541	0	0
T7	29233	102	0	0
T8	45210	102	0	0
T9	133758	205	0	0
T10	38746	61	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11550997	21772	0	0
T1	2147	6	0	0
T2	2584	6	0	0
T3	5089	8	0	0
T4	42340	102	0	0
T5	5472	8	0	0
T6	354431	541	0	0
T7	26050	102	0	0
T8	42044	102	0	0
T9	116368	205	0	0
T10	33648	61	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11550997	21772	0	0
T1	2147	6	0	0
T2	2584	6	0	0
T3	5089	8	0	0
T4	42340	102	0	0
T5	5472	8	0	0
T6	354431	541	0	0
T7	26050	102	0	0
T8	42044	102	0	0
T9	116368	205	0	0
T10	33648	61	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11550997	21772	0	0
T1	2147	6	0	0
T2	2584	6	0	0
T3	5089	8	0	0
T4	42340	102	0	0
T5	5472	8	0	0
T6	354431	541	0	0
T7	26050	102	0	0
T8	42044	102	0	0
T9	116368	205	0	0
T10	33648	61	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11550997	21772	0	0
T1	2147	6	0	0
T2	2584	6	0	0
T3	5089	8	0	0
T4	42340	102	0	0
T5	5472	8	0	0
T6	354431	541	0	0
T7	26050	102	0	0
T8	42044	102	0	0
T9	116368	205	0	0
T10	33648	61	0	0