Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T23,T26
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T26,T28
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T26,T28
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T26,T28
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T26,T28
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T26,T28
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T26,T28
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13007859	13888	0	0
gen_assertions[0].RstEnOn_A	13007859	1034	0	0
gen_assertions[0].RstNOff_A	13007859	13888	0	0
gen_assertions[0].RstNOn_A	13007859	1034	0	0
gen_assertions[1].RstEnOff_A	52030628	12601	0	0
gen_assertions[1].RstEnOn_A	52030628	1004	0	0
gen_assertions[1].RstNOff_A	52030628	12601	0	0
gen_assertions[1].RstNOn_A	52030628	1004	0	0
gen_assertions[2].RstEnOff_A	26016409	12676	0	0
gen_assertions[2].RstEnOn_A	26016409	1025	0	0
gen_assertions[2].RstNOff_A	26016409	12676	0	0
gen_assertions[2].RstNOn_A	26016409	1025	0	0
gen_assertions[3].RstEnOff_A	26016262	12688	0	0
gen_assertions[3].RstEnOn_A	26016262	1027	0	0
gen_assertions[3].RstNOff_A	26016262	12688	0	0
gen_assertions[3].RstNOn_A	26016262	1027	0	0
gen_assertions[4].RstEnOff_A	1641933	21577	0	0
gen_assertions[4].RstEnOn_A	1641933	1093	0	0
gen_assertions[4].RstNOff_A	1641933	21577	0	0
gen_assertions[4].RstNOn_A	1641933	1093	0	0
gen_assertions[5].RstEnOff_A	13007859	14140	0	0
gen_assertions[5].RstEnOn_A	13007859	1126	0	0
gen_assertions[5].RstNOff_A	13007859	14140	0	0
gen_assertions[5].RstNOn_A	13007859	1126	0	0
gen_assertions[6].RstEnOff_A	13007859	14212	0	0
gen_assertions[6].RstEnOn_A	13007859	1196	0	0
gen_assertions[6].RstNOff_A	13007859	14212	0	0
gen_assertions[6].RstNOn_A	13007859	1196	0	0
gen_assertions[7].RstEnOff_A	13007859	14228	0	0
gen_assertions[7].RstEnOn_A	13007859	1214	0	0
gen_assertions[7].RstNOff_A	13007859	14228	0	0
gen_assertions[7].RstNOn_A	13007859	1214	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	13888	0	0
T1	2386	4	0	0
T2	2778	5	0	0
T3	5826	0	0	0
T4	45597	75	0	0
T5	5824	0	0	0
T6	404350	0	0	0
T7	29233	75	0	0
T8	45210	75	0	0
T9	133758	151	0	0
T10	38746	40	0	0
T11	0	6	0	0
T13	0	23	0	0
T23	0	13	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	1034	0	0
T2	2778	1	0	0
T3	5826	0	0	0
T4	45597	0	0	0
T5	5824	0	0	0
T6	404350	0	0	0
T7	29233	0	0	0
T8	45210	0	0	0
T9	133758	15	0	0
T10	38746	0	0	0
T11	2565	1	0	0
T23	0	6	0	0
T24	0	3	0	0
T26	0	5	0	0
T28	0	45	0	0
T49	0	5	0	0
T50	0	1	0	0
T66	0	15	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	13888	0	0
T1	2386	4	0	0
T2	2778	5	0	0
T3	5826	0	0	0
T4	45597	75	0	0
T5	5824	0	0	0
T6	404350	0	0	0
T7	29233	75	0	0
T8	45210	75	0	0
T9	133758	151	0	0
T10	38746	40	0	0
T11	0	6	0	0
T13	0	23	0	0
T23	0	13	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	1034	0	0
T2	2778	1	0	0
T3	5826	0	0	0
T4	45597	0	0	0
T5	5824	0	0	0
T6	404350	0	0	0
T7	29233	0	0	0
T8	45210	0	0	0
T9	133758	15	0	0
T10	38746	0	0	0
T11	2565	1	0	0
T23	0	6	0	0
T24	0	3	0	0
T26	0	5	0	0
T28	0	45	0	0
T49	0	5	0	0
T50	0	1	0	0
T66	0	15	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52030628	12601	0	0
T1	9549	2	0	0
T2	11117	4	0	0
T3	23308	0	0	0
T4	182359	66	0	0
T5	23302	0	0	0
T6	161746	0	0	0
T7	116875	64	0	0
T8	180861	65	0	0
T9	535041	139	0	0
T10	155000	36	0	0
T11	0	6	0	0
T13	0	22	0	0
T23	0	11	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52030628	1004	0	0
T9	535041	14	0	0
T10	155000	0	0	0
T11	10269	0	0	0
T12	22182	0	0	0
T13	182245	0	0	0
T23	13622	3	0	0
T24	20958	0	0	0
T25	9285	0	0	0
T26	94033	5	0	0
T28	0	51	0	0
T39	5858	0	0	0
T49	0	7	0	0
T50	0	1	0	0
T66	0	14	0	0
T67	0	4	0	0
T68	0	3	0	0
T69	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52030628	12601	0	0
T1	9549	2	0	0
T2	11117	4	0	0
T3	23308	0	0	0
T4	182359	66	0	0
T5	23302	0	0	0
T6	161746	0	0	0
T7	116875	64	0	0
T8	180861	65	0	0
T9	535041	139	0	0
T10	155000	36	0	0
T11	0	6	0	0
T13	0	22	0	0
T23	0	11	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52030628	1004	0	0
T9	535041	14	0	0
T10	155000	0	0	0
T11	10269	0	0	0
T12	22182	0	0	0
T13	182245	0	0	0
T23	13622	3	0	0
T24	20958	0	0	0
T25	9285	0	0	0
T26	94033	5	0	0
T28	0	51	0	0
T39	5858	0	0	0
T49	0	7	0	0
T50	0	1	0	0
T66	0	14	0	0
T67	0	4	0	0
T68	0	3	0	0
T69	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016409	12676	0	0
T1	4772	2	0	0
T2	5556	4	0	0
T3	11648	0	0	0
T4	91200	66	0	0
T5	11656	0	0	0
T6	808792	0	0	0
T7	58441	64	0	0
T8	90427	65	0	0
T9	267509	138	0	0
T10	77504	36	0	0
T11	0	6	0	0
T13	0	22	0	0
T23	0	11	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016409	1025	0	0
T9	267509	14	0	0
T10	77504	0	0	0
T11	5134	0	0	0
T12	11091	0	0	0
T13	91119	0	0	0
T23	6811	0	0	0
T24	10479	0	0	0
T25	4642	0	0	0
T26	47025	6	0	0
T28	0	50	0	0
T39	2928	0	0	0
T49	0	10	0	0
T50	0	3	0	0
T56	0	1	0	0
T66	0	11	0	0
T67	0	4	0	0
T68	0	1	0	0
T69	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016409	12676	0	0
T1	4772	2	0	0
T2	5556	4	0	0
T3	11648	0	0	0
T4	91200	66	0	0
T5	11656	0	0	0
T6	808792	0	0	0
T7	58441	64	0	0
T8	90427	65	0	0
T9	267509	138	0	0
T10	77504	36	0	0
T11	0	6	0	0
T13	0	22	0	0
T23	0	11	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016409	1025	0	0
T9	267509	14	0	0
T10	77504	0	0	0
T11	5134	0	0	0
T12	11091	0	0	0
T13	91119	0	0	0
T23	6811	0	0	0
T24	10479	0	0	0
T25	4642	0	0	0
T26	47025	6	0	0
T28	0	50	0	0
T39	2928	0	0	0
T49	0	10	0	0
T50	0	3	0	0
T56	0	1	0	0
T66	0	11	0	0
T67	0	4	0	0
T68	0	1	0	0
T69	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016262	12688	0	0
T1	4775	2	0	0
T2	5559	4	0	0
T3	11647	0	0	0
T4	91184	66	0	0
T5	11649	0	0	0
T6	808847	0	0	0
T7	58452	64	0	0
T8	90438	65	0	0
T9	267501	137	0	0
T10	77501	36	0	0
T11	0	6	0	0
T13	0	22	0	0
T23	0	11	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016262	1027	0	0
T9	267501	12	0	0
T10	77501	0	0	0
T11	5134	0	0	0
T12	11091	0	0	0
T13	91129	0	0	0
T23	6812	0	0	0
T24	10479	0	0	0
T25	4643	0	0	0
T26	47031	5	0	0
T28	0	48	0	0
T39	2928	0	0	0
T49	0	10	0	0
T50	0	4	0	0
T51	0	11	0	0
T66	0	13	0	0
T67	0	5	0	0
T69	0	1	0	0
T70	0	29	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016262	12688	0	0
T1	4775	2	0	0
T2	5559	4	0	0
T3	11647	0	0	0
T4	91184	66	0	0
T5	11649	0	0	0
T6	808847	0	0	0
T7	58452	64	0	0
T8	90438	65	0	0
T9	267501	137	0	0
T10	77501	36	0	0
T11	0	6	0	0
T13	0	22	0	0
T23	0	11	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26016262	1027	0	0
T9	267501	12	0	0
T10	77501	0	0	0
T11	5134	0	0	0
T12	11091	0	0	0
T13	91129	0	0	0
T23	6812	0	0	0
T24	10479	0	0	0
T25	4643	0	0	0
T26	47031	5	0	0
T28	0	48	0	0
T39	2928	0	0	0
T49	0	10	0	0
T50	0	4	0	0
T51	0	11	0	0
T66	0	13	0	0
T67	0	5	0	0
T69	0	1	0	0
T70	0	29	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641933	21577	0	0
T1	297	4	0	0
T2	346	6	0	0
T3	730	3	0	0
T4	5714	93	0	0
T5	730	3	0	0
T6	50795	541	0	0
T7	3668	76	0	0
T8	5665	87	0	0
T9	16945	217	0	0
T10	4908	61	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641933	1093	0	0
T9	16945	14	0	0
T10	4908	0	0	0
T11	319	0	0	0
T12	693	0	0	0
T13	5760	0	0	0
T23	424	0	0	0
T24	654	0	0	0
T25	288	0	0	0
T26	3008	4	0	0
T28	0	44	0	0
T39	182	0	0	0
T49	0	10	0	0
T50	0	4	0	0
T51	0	10	0	0
T56	0	1	0	0
T66	0	11	0	0
T67	0	6	0	0
T69	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641933	21577	0	0
T1	297	4	0	0
T2	346	6	0	0
T3	730	3	0	0
T4	5714	93	0	0
T5	730	3	0	0
T6	50795	541	0	0
T7	3668	76	0	0
T8	5665	87	0	0
T9	16945	217	0	0
T10	4908	61	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1641933	1093	0	0
T9	16945	14	0	0
T10	4908	0	0	0
T11	319	0	0	0
T12	693	0	0	0
T13	5760	0	0	0
T23	424	0	0	0
T24	654	0	0	0
T25	288	0	0	0
T26	3008	4	0	0
T28	0	44	0	0
T39	182	0	0	0
T49	0	10	0	0
T50	0	4	0	0
T51	0	10	0	0
T56	0	1	0	0
T66	0	11	0	0
T67	0	6	0	0
T69	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	14140	0	0
T1	2386	4	0	0
T2	2778	4	0	0
T3	5826	0	0	0
T4	45597	75	0	0
T5	5824	0	0	0
T6	404350	0	0	0
T7	29233	75	0	0
T8	45210	75	0	0
T9	133758	150	0	0
T10	38746	40	0	0
T11	0	6	0	0
T13	0	23	0	0
T23	0	13	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	1126	0	0
T9	133758	12	0	0
T10	38746	0	0	0
T11	2565	0	0	0
T12	5544	0	0	0
T13	45558	0	0	0
T23	3405	0	0	0
T24	5239	0	0	0
T25	2320	0	0	0
T26	23511	5	0	0
T28	0	52	0	0
T39	1464	0	0	0
T49	0	10	0	0
T50	0	5	0	0
T51	0	11	0	0
T66	0	16	0	0
T67	0	4	0	0
T69	0	2	0	0
T70	0	25	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	14140	0	0
T1	2386	4	0	0
T2	2778	4	0	0
T3	5826	0	0	0
T4	45597	75	0	0
T5	5824	0	0	0
T6	404350	0	0	0
T7	29233	75	0	0
T8	45210	75	0	0
T9	133758	150	0	0
T10	38746	40	0	0
T11	0	6	0	0
T13	0	23	0	0
T23	0	13	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	1126	0	0
T9	133758	12	0	0
T10	38746	0	0	0
T11	2565	0	0	0
T12	5544	0	0	0
T13	45558	0	0	0
T23	3405	0	0	0
T24	5239	0	0	0
T25	2320	0	0	0
T26	23511	5	0	0
T28	0	52	0	0
T39	1464	0	0	0
T49	0	10	0	0
T50	0	5	0	0
T51	0	11	0	0
T66	0	16	0	0
T67	0	4	0	0
T69	0	2	0	0
T70	0	25	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	14212	0	0
T1	2386	4	0	0
T2	2778	4	0	0
T3	5826	0	0	0
T4	45597	75	0	0
T5	5824	0	0	0
T6	404350	0	0	0
T7	29233	75	0	0
T8	45210	75	0	0
T9	133758	151	0	0
T10	38746	40	0	0
T11	0	6	0	0
T13	0	23	0	0
T23	0	13	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	1196	0	0
T9	133758	14	0	0
T10	38746	0	0	0
T11	2565	0	0	0
T12	5544	0	0	0
T13	45558	0	0	0
T23	3405	0	0	0
T24	5239	0	0	0
T25	2320	0	0	0
T26	23511	5	0	0
T28	0	49	0	0
T39	1464	0	0	0
T49	0	14	0	0
T50	0	6	0	0
T51	0	13	0	0
T56	0	1	0	0
T66	0	13	0	0
T67	0	6	0	0
T69	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	14212	0	0
T1	2386	4	0	0
T2	2778	4	0	0
T3	5826	0	0	0
T4	45597	75	0	0
T5	5824	0	0	0
T6	404350	0	0	0
T7	29233	75	0	0
T8	45210	75	0	0
T9	133758	151	0	0
T10	38746	40	0	0
T11	0	6	0	0
T13	0	23	0	0
T23	0	13	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	1196	0	0
T9	133758	14	0	0
T10	38746	0	0	0
T11	2565	0	0	0
T12	5544	0	0	0
T13	45558	0	0	0
T23	3405	0	0	0
T24	5239	0	0	0
T25	2320	0	0	0
T26	23511	5	0	0
T28	0	49	0	0
T39	1464	0	0	0
T49	0	14	0	0
T50	0	6	0	0
T51	0	13	0	0
T56	0	1	0	0
T66	0	13	0	0
T67	0	6	0	0
T69	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	14228	0	0
T1	2386	4	0	0
T2	2778	4	0	0
T3	5826	0	0	0
T4	45597	75	0	0
T5	5824	0	0	0
T6	404350	0	0	0
T7	29233	75	0	0
T8	45210	75	0	0
T9	133758	148	0	0
T10	38746	40	0	0
T11	0	6	0	0
T13	0	23	0	0
T23	0	13	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	1214	0	0
T9	133758	11	0	0
T10	38746	0	0	0
T11	2565	0	0	0
T12	5544	0	0	0
T13	45558	0	0	0
T23	3405	0	0	0
T24	5239	0	0	0
T25	2320	0	0	0
T26	23511	7	0	0
T28	0	48	0	0
T39	1464	0	0	0
T49	0	14	0	0
T50	0	7	0	0
T51	0	14	0	0
T66	0	14	0	0
T67	0	5	0	0
T69	0	4	0	0
T70	0	30	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	14228	0	0
T1	2386	4	0	0
T2	2778	4	0	0
T3	5826	0	0	0
T4	45597	75	0	0
T5	5824	0	0	0
T6	404350	0	0	0
T7	29233	75	0	0
T8	45210	75	0	0
T9	133758	148	0	0
T10	38746	40	0	0
T11	0	6	0	0
T13	0	23	0	0
T23	0	13	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13007859	1214	0	0
T9	133758	11	0	0
T10	38746	0	0	0
T11	2565	0	0	0
T12	5544	0	0	0
T13	45558	0	0	0
T23	3405	0	0	0
T24	5239	0	0	0
T25	2320	0	0	0
T26	23511	7	0	0
T28	0	48	0	0
T39	1464	0	0	0
T49	0	14	0	0
T50	0	7	0	0
T51	0	14	0	0
T66	0	14	0	0
T67	0	5	0	0
T69	0	4	0	0
T70	0	30	0	0