Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12259415	6637	0	0
alert_regwen_rd_A	12259415	4899	0	0
cpu_regwen_rd_A	12259415	4796	0	0
sw_rst_ctrl_n_0_rd_A	12259415	8665	0	0
sw_rst_ctrl_n_1_rd_A	12259415	8988	0	0
sw_rst_ctrl_n_2_rd_A	12259415	8910	0	0
sw_rst_ctrl_n_3_rd_A	12259415	9240	0	0
sw_rst_ctrl_n_4_rd_A	12259415	9023	0	0
sw_rst_ctrl_n_5_rd_A	12259415	8879	0	0
sw_rst_ctrl_n_6_rd_A	12259415	9169	0	0
sw_rst_ctrl_n_7_rd_A	12259415	8892	0	0
sw_rst_regwen_0_rd_A	12259415	5456	0	0
sw_rst_regwen_1_rd_A	12259415	5519	0	0
sw_rst_regwen_2_rd_A	12259415	5503	0	0
sw_rst_regwen_3_rd_A	12259415	5454	0	0
sw_rst_regwen_4_rd_A	12259415	5504	0	0
sw_rst_regwen_5_rd_A	12259415	5428	0	0
sw_rst_regwen_6_rd_A	12259415	5506	0	0
sw_rst_regwen_7_rd_A	12259415	5618	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	6637	0	0
T55	4671	21	0	0
T57	2120	211	0	0
T58	6713	280	0	0
T62	11169	1	0	0
T73	9492	551	0	0
T74	2562	269	0	0
T75	3068	10	0	0
T76	21095	2	0	0
T79	19506	3	0	0
T81	20382	4	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	4899	0	0
T13	41085	74	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	0	0	0
T67	0	83	0	0
T82	0	44	0	0
T84	0	26	0	0
T87	0	647	0	0
T88	0	282	0	0
T90	0	47	0	0
T93	0	193	0	0
T110	0	49	0	0
T111	0	72	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	4796	0	0
T13	41085	75	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	0	0	0
T67	0	93	0	0
T82	0	41	0	0
T84	0	24	0	0
T87	0	578	0	0
T88	0	252	0	0
T90	0	42	0	0
T93	0	185	0	0
T110	0	27	0	0
T111	0	42	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	8665	0	0
T13	41085	61	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	108	0	0
T56	0	13	0	0
T66	0	106	0	0
T67	0	117	0	0
T82	0	47	0	0
T84	0	18	0	0
T90	0	28	0	0
T112	0	215	0	0
T113	0	15	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	8988	0	0
T13	41085	95	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	109	0	0
T56	0	11	0	0
T66	0	87	0	0
T67	0	158	0	0
T82	0	58	0	0
T84	0	46	0	0
T90	0	33	0	0
T112	0	218	0	0
T113	0	20	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	8910	0	0
T13	41085	97	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	139	0	0
T56	0	18	0	0
T66	0	109	0	0
T67	0	143	0	0
T82	0	48	0	0
T84	0	37	0	0
T90	0	50	0	0
T112	0	214	0	0
T113	0	8	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	9240	0	0
T13	41085	88	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	131	0	0
T56	0	21	0	0
T66	0	138	0	0
T67	0	131	0	0
T82	0	56	0	0
T84	0	38	0	0
T90	0	32	0	0
T112	0	222	0	0
T113	0	9	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	9023	0	0
T13	41085	84	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	113	0	0
T56	0	23	0	0
T66	0	123	0	0
T67	0	177	0	0
T82	0	50	0	0
T84	0	49	0	0
T90	0	42	0	0
T112	0	153	0	0
T113	0	11	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	8879	0	0
T13	41085	62	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	102	0	0
T56	0	10	0	0
T66	0	98	0	0
T67	0	110	0	0
T82	0	67	0	0
T84	0	15	0	0
T90	0	47	0	0
T112	0	232	0	0
T113	0	6	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	9169	0	0
T13	41085	94	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	117	0	0
T56	0	12	0	0
T66	0	93	0	0
T67	0	122	0	0
T82	0	49	0	0
T84	0	19	0	0
T90	0	41	0	0
T112	0	198	0	0
T113	0	14	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	8892	0	0
T13	41085	103	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	128	0	0
T56	0	16	0	0
T66	0	125	0	0
T67	0	132	0	0
T82	0	58	0	0
T84	0	37	0	0
T90	0	54	0	0
T112	0	233	0	0
T113	0	9	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	5456	0	0
T13	41085	78	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	18	0	0
T56	0	2	0	0
T67	0	62	0	0
T82	0	47	0	0
T84	0	43	0	0
T90	0	48	0	0
T112	0	42	0	0
T113	0	10	0	0
T114	0	35	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	5519	0	0
T13	41085	85	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	11	0	0
T56	0	4	0	0
T67	0	112	0	0
T82	0	66	0	0
T84	0	39	0	0
T90	0	46	0	0
T112	0	41	0	0
T113	0	11	0	0
T114	0	25	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	5503	0	0
T13	41085	98	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	11	0	0
T56	0	7	0	0
T67	0	104	0	0
T82	0	64	0	0
T84	0	26	0	0
T90	0	38	0	0
T112	0	27	0	0
T113	0	15	0	0
T114	0	17	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	5454	0	0
T13	41085	88	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	12	0	0
T56	0	9	0	0
T67	0	110	0	0
T82	0	52	0	0
T84	0	31	0	0
T90	0	40	0	0
T112	0	22	0	0
T113	0	8	0	0
T114	0	24	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	5504	0	0
T13	41085	91	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	21	0	0
T56	0	6	0	0
T67	0	84	0	0
T82	0	41	0	0
T84	0	18	0	0
T90	0	52	0	0
T112	0	40	0	0
T113	0	3	0	0
T114	0	22	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	5428	0	0
T13	41085	117	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	13	0	0
T56	0	10	0	0
T67	0	111	0	0
T82	0	52	0	0
T84	0	24	0	0
T90	0	55	0	0
T112	0	25	0	0
T113	0	7	0	0
T114	0	22	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	5506	0	0
T13	41085	72	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	11	0	0
T56	0	10	0	0
T67	0	59	0	0
T82	0	45	0	0
T84	0	21	0	0
T90	0	40	0	0
T112	0	22	0	0
T113	0	12	0	0
T114	0	37	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259415	5618	0	0
T13	41085	91	0	0
T23	2356	0	0	0
T24	4201	0	0	0
T25	2079	0	0	0
T26	19126	0	0	0
T27	391308	0	0	0
T28	167313	0	0	0
T29	5474	0	0	0
T30	4253	0	0	0
T49	10209	29	0	0
T56	0	10	0	0
T67	0	93	0	0
T82	0	69	0	0
T84	0	33	0	0
T90	0	14	0	0
T112	0	28	0	0
T113	0	18	0	0
T114	0	36	0	0